IBM technology for building transistors from silicon nanosheets will enable 5nm chips

June 18, 2017
Source: ASM International

IBM, Armonk, N.Y., announces the development of the first industry process for building silicon nanosheet transistors that will enable 5nm chips. Less than two years after developing a 7nm test node chip with 20 billion transistors, scientists have paved the way for 30 billion switches on a fingernail-sized chip. 

The resulting increase in performance will help accelerate cognitive computing, the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today's devices, before needing to be charged.

IBM scientists worked on this development, together with Research Alliance partners Global Foundries and Samsung, and various equipment suppliers, at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering's NanoTech Complex in Albany, N.Y. They achieved the breakthrough by using stacks of silicon nanosheets as the device structure of the transistor, instead of the standard FinFET architecture, which has been the blueprint for the semiconductor industry up through 7nm node technology.

The silicon nanosheet transistor demonstration was detailed in the Research Alliance paper, "Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET." It was published by VLSI, and proves that 5nm chips are possible, more powerful, and not too far off in the future.

Compared to the leading-edge 10nm technology available in the market, a nanosheet-based 5nm technology can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. This improvement enables a significant boost to meeting the future demands of artificial intelligence systems, virtual reality, and mobile devices.

This same Extreme Ultraviolet (EUV) lithography approach that produces the 7nm test node and its 20 billion transistors, was applied to the nanosheet transistor architecture. With EUV lithography, the width of the nanosheets can be adjusted continuously, all within a single manufacturing process or chip design.

This adjustability permits the fine-tuning of performance and power for specific circuits – something not possible with today's FinFET transistor architecture production, which is limited by its current-carrying fin height. Therefore, while FinFET chips can scale to 5nm, simply reducing the amount of space between fins does not provide increased current flow for additional performance.



Subject Classifications

Industries and Applications | Electronics

Industries and Applications | Nanotechnology