- November 5-9, 2017
- Pasadena Convention Center
- Pasadena, CA, USA
ISTFA's 2017 General Info
Plan today to attend ISTFA 2017! This year's theme is ‘Striving for 100% Success Rate'
We are currently accepting papers for the technical program of the 43rd International Symposium for Testing and Failure Analysis (ISTFA). Paper selection is based entirely on information submitted in abstracts and will be evaluated on novelty, completeness, quality, and benefit to the FA community. Submit your minimum two-page abstract including images, figures, and references.
The Call for Papers has been extended!
Deadline for Abstract Submission:
April 21, 2017 April 28, 2017
The value of Failure Analysis is fully realized when the root cause of problem successfully identified in a timely manner. The process of performing failure analysis often requires irreversible operations to the failing device. Every day, failure analysts are challenged to perform operations on the failing device without altering the functionality of the device or destroying the physical evidence of the defect. New products and technologies add extra dimensions to this challenge. The International Symposium for Testing and Failure Analysis (ISTFA) offers the best venue to failure analysts for acquiring the knowledge and the resources needed to take on these challenges. At ISTFA, you can learn from the experts about the tools and techniques needed for maximizing Success Rate in every aspect of Electronic Device Failure Analysis process. You can network with other failure analysts who can offer critical technical advice, and you will learn about state-of-art tools to meet your analysis challenges at the exposition. You can also participate as an expert presenter, teaching your novel idea or technique to the FA community.
How to Educate the Next Generation IC Debug / FA Engineer at Academia
Next Generation of FA Engineers
VLP… Demonstrating 110 nm Resolution in Common Laser Probing Applications
Dr. Travis Eiles, Intel Corporation
Root Cause Analysis for Pin Leakage
Dr. Zhigang Song, GLOBALFOUNDRIES
Validation of DLS data by LVP in case of marginal failure
Keonil Kim, Samsung Electronics S.SLI division
Sample Preparation Challenges in removing Copper Pillar WLCSP Device Embedded in PCB Module for Electrical Testing and Failure Analysis
Kah Chin Cheong, ON Semiconductor
Best Student Poster
Solder Ball Reliability Assessment of WLCSP Through Power Cycling
Bhavna Conjeevaram, University of Texas Arlington
ACETONEMENT aka: Where did the Bond Wires Go?
Timothy Hazeldine, ULTRA TEC