{"id":3808,"date":"2019-09-18T12:30:16","date_gmt":"2019-09-18T12:30:16","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/38331481\/NEWS\/"},"modified":"2023-02-07T04:52:39","modified_gmt":"2023-02-07T04:52:39","slug":"cerebras-systems-develops-wafer-scale-engine-chip-with-1-2-trillion-transistors","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/38331481\/NEWS\/","title":{"rendered":"Cerebras Systems develops wafer scale engine chip with 1.2 trillion transistors"},"content":{"rendered":"<p style=\"margin-bottom:.0001pt\"><span style=\"line-height:normal\">Cerebras Systems, Los Altos, Calif., a startup dedicated to accelerating artificial intelligence computing, announces that it has developed the largest chip ever built: a WSE chip with 71.6 square inches of area. <\/span><\/p>\n<p style=\"margin-bottom:.0001pt\">&nbsp;<\/p>\n<p style=\"margin-bottom:.0001pt\"><span style=\"line-height:normal\">Optimized for AI work, the Cerebras wafer scale engine (WSE) is a single chip that contains more than 1.2 trillion transistors and 46,225 square millimeters (71.6 square inches) in area. The WSE is 56.7 times larger than the largest graphics processing unit, which measures 815 square millimeters (1.26 square inches) and 21.1 billion transistors. The WSE also contains 3000 times more high-speed, on-chip memory, and has 10,000 times more memory bandwidth.<\/span><\/p>\n<p style=\"margin-bottom:.0001pt\">&nbsp;<\/p>\n<p style=\"margin-bottom:.0001pt\"><span style=\"line-height:normal\">With vastly more silicon area than the largest graphics processing unit, the WSE provides more compute cores, tightly coupled memory for efficient data access, and an extensive high bandwidth communication fabric for groups of cores to work together.<\/span><\/p>\n<p style=\"margin-bottom:.0001pt\">&nbsp;<\/p>\n<p style=\"margin-bottom:.0001pt\"><span style=\"line-height:normal\">The WSE contains 400,000 Sparse Linear Algebra (SLA) cores. Each core is flexible, programmable, and optimized for the computations that underpin most neural networks. Programmability ensures the cores can run all algorithms in the constantly changing machine learning field.<\/span><\/p>\n<p style=\"margin-bottom:.0001pt\">&nbsp;<\/p>\n<p style=\"margin-bottom:.0001pt\"><span style=\"line-height:normal\">The 400,000 cores on the WSE are connected via the Swarm communication fabric in a 2D mesh with 100 Pb\/s of bandwidth. Swarm is a massive on-chip communication fabric that delivers breakthrough bandwidth and low latency at a fraction of the power draw of traditional techniques used to cluster graphics processing units. It is fully configurable; software configures all the cores on the WSE to support the precise communication required for training the user-specified model. For each neural network, Swarm provides a unique and optimized communication path.<\/span><\/p>\n<p style=\"margin-bottom:.0001pt\">&nbsp;<\/p>\n<p style=\"margin-bottom:.0001pt\"><span style=\"line-height:normal\"><a href=\"http:\/\/www.cerebras.net\">www.cerebras.net<\/a> <\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Cerebras Systems, Los Altos, Calif., a startup dedicated to accelerating artificial intelligence computing, announces that it has developed the largest chip ever built: a WSE chip with 71.6 square inches of area.<\/p>\n","protected":false},"author":63082,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[434,438,435,436,1],"tags":[],"class_list":["post-3808","post","type-post","status-publish","format-standard","hentry","category-electronics","category-nanotechnology","category-news","category-news-articles","category-uncategorized"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.9 - 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