{"id":4010,"date":"2017-03-20T11:44:56","date_gmt":"2017-03-20T11:44:56","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/27261864\/NEWS\/"},"modified":"2023-02-07T04:52:54","modified_gmt":"2023-02-07T04:52:54","slug":"cadence-to-collaborate-with-tsmc-for-design-innovation-with-its-12ffc-process","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/27261864\/NEWS\/","title":{"rendered":"Cadence to collaborate with TSMC for design innovation with its 12FFC process"},"content":{"rendered":"<p>\n\tCadence Design Systems Inc., San Jose, Calif., announces its collaboration with the Taiwan Semiconductor Manufacturing Co. (TSMC) to further advanced-node design innovation with TSMC&#8217;s new 12nm FinFET Compact (12FFC) process technology. With Cadence digital and signoff solutions, custom\/analog solutions and IP, system-on-chip, designers can use the 12FFC process to create emerging mid-range mobile and high-end consumer applications that require optimal power, performance, and area. Cadence is actively working with customers on early engagements with the 12FFC process.<\/p>\n<p>\n\tIn support of TSMC&#8217;s new 12FFC process technology, Cadence digital and signoff and custom\/analog tools have achieved the latest version of Design Rule Manual certification for the TSMC 12FFC process. A corresponding process design kit is also available for download. Additionally, Cadence has delivered a library characterization tool flow and is developing IP for customers migrating to the 12FFC process.<\/p>\n<p>\n\tThe Cadence digital and signoff tools provide floorplanning, placement, routing and extraction enhancements required for the 12FFC process technology. The Cadence custom\/analog tools provide underlying support and capabilities that enable designers to improve productivity when compared with traditional, manual approaches as well as fast, accurate verification of 12FFC design performance and reliability<\/p>\n<p>\n\t<a href=\"http:\/\/www.cadence.com\/go\/tsmc12ffcds\">www.cadence.com\/go\/tsmc12ffcds<\/a><\/p>\n<p>\n\t&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Cadence Design Systems Inc., San Jose, Calif., announces its collaboration with the Taiwan Semiconductor Manufacturing Co. (TSMC) to further advanced-node design innovation with TSMC&#8217;s new 12nm FinFET Compact (12FFC) process technology.<\/p>\n","protected":false},"author":63082,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[434,450,438,435,436,1],"tags":[],"class_list":["post-4010","post","type-post","status-publish","format-standard","hentry","category-electronics","category-general","category-nanotechnology","category-news","category-news-articles","category-uncategorized"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.9 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Cadence to collaborate with TSMC for design innovation with its 12FFC process - Electronic Device Failure Analysis Society<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/27261864\/NEWS\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Cadence to collaborate with TSMC for design innovation with its 12FFC process - Electronic Device Failure Analysis Society\" \/>\n<meta property=\"og:description\" content=\"Cadence Design Systems Inc., San Jose, Calif., announces its collaboration with the Taiwan Semiconductor Manufacturing Co. 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