{"id":4115,"date":"2016-07-25T21:31:56","date_gmt":"2016-07-25T21:31:56","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/"},"modified":"2023-02-07T04:53:02","modified_gmt":"2023-02-07T04:53:02","slug":"cadence-announces-intel-certified-implementation-and-signoff-tools","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/","title":{"rendered":"Cadence announces Intel- certified implementation and signoff tools"},"content":{"rendered":"<p>\n\tCadence Design Systems Inc., San Jose, Calif., announces that its implementation and signoff tools have achieved certification on the Intel third-generation 10 nm tri-gate process for customers of Intel Custom Foundry. Intel utilized a PowerVR GT7200 graphics processing unit (GPU) from Imagination Technologies as part of the certification process.<\/p>\n<p>\n\tThe tool certification and enablement provide Intel Custom Foundry customers with a complete and integrated system-on-chip (SoC) design flow.<\/p>\n<p>\n\tCadence tools in the flow include:<\/p>\n<p>\n\tInnovus Implementation System<\/p>\n<p>\n\tQuantus QRC Extraction Solution<\/p>\n<p>\n\tTempus Timing Signoff Solution<\/p>\n<p>\n\tVoltus IC Power Integrity Solution.<\/p>\n<p>\n\tVoltus-Fi Custom Power Integrity Solution<\/p>\n<p>\n\tSpectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS) and Spectre RF Simulation.<\/p>\n<p>\n\tFor more information on the Cadence tools that are certified, please visit&nbsp;<a href=\"http:\/\/www.cadence.com\/go\/icf10nm\">cadence.com\/go\/icf10nm<\/a>, and for more information on Intel Custom Foundry, please visit <a href=\"http:\/\/www.intel.com\/content\/www\/us\/en\/foundry\/overview.html\">intel.com\/foundry<\/a>.<\/p>\n<p>\n\t&#8220;Intel Custom Foundry has worked closely with Cadence to deliver an optimized design ecosystem for our customers who are creating innovative, advanced-node designs,&#8221; said Dr. Changhong Dai, vice president, Technology and Manufacturing Group, and director, Technology Optimization Solutions at Intel. &#8220;The certified Cadence digital implementation, signoff and simulation tools offer our mutual customers a complete and integrated flow and help them achieve superior PPA on Intel&#8217;s third-generation tri-gate 10nm process technology.&#8221;&nbsp;<\/p>\n<p>\n\t<a href=\"http:\/\/www.cadence.com\/\">www.cadence.com<\/a><\/p>\n<p>\n\t&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Cadence Design Systems Inc., San Jose, Calif., announces that its implementation and signoff tools have achieved certification on the Intel third-generation 10 nm tri-gate process for customers of Intel Custom Foundry.<\/p>\n","protected":false},"author":63082,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[434,450,438,435,436,1],"tags":[],"class_list":["post-4115","post","type-post","status-publish","format-standard","hentry","category-electronics","category-general","category-nanotechnology","category-news","category-news-articles","category-uncategorized"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.9 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Cadence announces Intel- certified implementation and signoff tools - Electronic Device Failure Analysis Society<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Cadence announces Intel- certified implementation and signoff tools - Electronic Device Failure Analysis Society\" \/>\n<meta property=\"og:description\" content=\"Cadence Design Systems Inc., San Jose, Calif., announces that its implementation and signoff tools have achieved certification on the Intel third-generation 10 nm tri-gate process for customers of Intel Custom Foundry.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/\" \/>\n<meta property=\"og:site_name\" content=\"Electronic Device Failure Analysis Society\" \/>\n<meta property=\"article:published_time\" content=\"2016-07-25T21:31:56+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2023-02-07T04:53:02+00:00\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/results\\\/-\\\/journal_content\\\/56\\\/10192\\\/26712321\\\/NEWS\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/results\\\/-\\\/journal_content\\\/56\\\/10192\\\/26712321\\\/NEWS\\\/\"},\"author\":{\"name\":\"\",\"@id\":\"\"},\"headline\":\"Cadence announces Intel- certified implementation and signoff tools\",\"datePublished\":\"2016-07-25T21:31:56+00:00\",\"dateModified\":\"2023-02-07T04:53:02+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/results\\\/-\\\/journal_content\\\/56\\\/10192\\\/26712321\\\/NEWS\\\/\"},\"wordCount\":222,\"publisher\":{\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/#organization\"},\"articleSection\":[\"Electronics\",\"general\",\"Nanotechnology\",\"news\",\"News Articles\"],\"inLanguage\":\"en-US\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/results\\\/-\\\/journal_content\\\/56\\\/10192\\\/26712321\\\/NEWS\\\/\",\"url\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/results\\\/-\\\/journal_content\\\/56\\\/10192\\\/26712321\\\/NEWS\\\/\",\"name\":\"Cadence announces Intel- certified implementation and signoff tools - Electronic Device Failure Analysis Society\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/#website\"},\"datePublished\":\"2016-07-25T21:31:56+00:00\",\"dateModified\":\"2023-02-07T04:53:02+00:00\",\"breadcrumb\":{\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/results\\\/-\\\/journal_content\\\/56\\\/10192\\\/26712321\\\/NEWS\\\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/results\\\/-\\\/journal_content\\\/56\\\/10192\\\/26712321\\\/NEWS\\\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/results\\\/-\\\/journal_content\\\/56\\\/10192\\\/26712321\\\/NEWS\\\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Cadence announces Intel- certified implementation and signoff tools\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/#website\",\"url\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/\",\"name\":\"Electronic Device Failure Analysis Society\",\"description\":\"Electronic Device Failure Analysis Society\",\"publisher\":{\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Organization\",\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/#organization\",\"name\":\"Electronic Device Failure Analysis Society\",\"url\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/#\\\/schema\\\/logo\\\/image\\\/\",\"url\":\"https:\\\/\\\/cdn-prd-main.asm-media.cloud\\\/uploads\\\/sites\\\/41\\\/2022\\\/10\\\/layout_set_logo.png\",\"contentUrl\":\"https:\\\/\\\/cdn-prd-main.asm-media.cloud\\\/uploads\\\/sites\\\/41\\\/2022\\\/10\\\/layout_set_logo.png\",\"width\":360,\"height\":95,\"caption\":\"Electronic Device Failure Analysis Society\"},\"image\":{\"@id\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/#\\\/schema\\\/logo\\\/image\\\/\"}},{\"@type\":\"Person\",\"@id\":\"\",\"url\":\"https:\\\/\\\/www.asminternational.org\\\/edfas\\\/author\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Cadence announces Intel- certified implementation and signoff tools - Electronic Device Failure Analysis Society","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/","og_locale":"en_US","og_type":"article","og_title":"Cadence announces Intel- certified implementation and signoff tools - Electronic Device Failure Analysis Society","og_description":"Cadence Design Systems Inc., San Jose, Calif., announces that its implementation and signoff tools have achieved certification on the Intel third-generation 10 nm tri-gate process for customers of Intel Custom Foundry.","og_url":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/","og_site_name":"Electronic Device Failure Analysis Society","article_published_time":"2016-07-25T21:31:56+00:00","article_modified_time":"2023-02-07T04:53:02+00:00","twitter_card":"summary_large_image","twitter_misc":{"Written by":"","Est. reading time":"1 minute"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/#article","isPartOf":{"@id":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/"},"author":{"name":"","@id":""},"headline":"Cadence announces Intel- certified implementation and signoff tools","datePublished":"2016-07-25T21:31:56+00:00","dateModified":"2023-02-07T04:53:02+00:00","mainEntityOfPage":{"@id":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/"},"wordCount":222,"publisher":{"@id":"https:\/\/www.asminternational.org\/edfas\/#organization"},"articleSection":["Electronics","general","Nanotechnology","news","News Articles"],"inLanguage":"en-US"},{"@type":"WebPage","@id":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/","url":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/","name":"Cadence announces Intel- certified implementation and signoff tools - Electronic Device Failure Analysis Society","isPartOf":{"@id":"https:\/\/www.asminternational.org\/edfas\/#website"},"datePublished":"2016-07-25T21:31:56+00:00","dateModified":"2023-02-07T04:53:02+00:00","breadcrumb":{"@id":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26712321\/NEWS\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.asminternational.org\/edfas\/"},{"@type":"ListItem","position":2,"name":"Cadence announces Intel- certified implementation and signoff tools"}]},{"@type":"WebSite","@id":"https:\/\/www.asminternational.org\/edfas\/#website","url":"https:\/\/www.asminternational.org\/edfas\/","name":"Electronic Device Failure Analysis Society","description":"Electronic Device Failure Analysis Society","publisher":{"@id":"https:\/\/www.asminternational.org\/edfas\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.asminternational.org\/edfas\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/www.asminternational.org\/edfas\/#organization","name":"Electronic Device Failure Analysis Society","url":"https:\/\/www.asminternational.org\/edfas\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/www.asminternational.org\/edfas\/#\/schema\/logo\/image\/","url":"https:\/\/cdn-prd-main.asm-media.cloud\/uploads\/sites\/41\/2022\/10\/layout_set_logo.png","contentUrl":"https:\/\/cdn-prd-main.asm-media.cloud\/uploads\/sites\/41\/2022\/10\/layout_set_logo.png","width":360,"height":95,"caption":"Electronic Device Failure Analysis Society"},"image":{"@id":"https:\/\/www.asminternational.org\/edfas\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"","url":"https:\/\/www.asminternational.org\/edfas\/author\/"}]}},"acf":[],"_links":{"self":[{"href":"https:\/\/www.asminternational.org\/edfas\/wp-json\/wp\/v2\/posts\/4115","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.asminternational.org\/edfas\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.asminternational.org\/edfas\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.asminternational.org\/edfas\/wp-json\/wp\/v2\/users\/63082"}],"replies":[{"embeddable":true,"href":"https:\/\/www.asminternational.org\/edfas\/wp-json\/wp\/v2\/comments?post=4115"}],"version-history":[{"count":0,"href":"https:\/\/www.asminternational.org\/edfas\/wp-json\/wp\/v2\/posts\/4115\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.asminternational.org\/edfas\/wp-json\/wp\/v2\/media?parent=4115"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.asminternational.org\/edfas\/wp-json\/wp\/v2\/categories?post=4115"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.asminternational.org\/edfas\/wp-json\/wp\/v2\/tags?post=4115"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}