{"id":4166,"date":"2016-03-19T20:34:11","date_gmt":"2016-03-19T20:34:11","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26219221\/NEWS\/"},"modified":"2023-02-07T04:53:06","modified_gmt":"2023-02-07T04:53:06","slug":"cadence-develops-design-and-analysis-solution-for-wafer-level-chip-scale-packaging","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/26219221\/NEWS\/","title":{"rendered":"Cadence develops design and analysis solution for wafer-level chip scale packaging"},"content":{"rendered":"<p>\n\t<span style=\"font-family: Helvetica, Arial, sans-serif; font-size: 0.9375em; font-weight: 400; line-height: 1.33333em;\">Cadence Design Systems Inc., San Jose, Calif., offers a foundry-proven IC packaging design and analysis solution for advanced fan-out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs. The new capabilities enable the faster multi-chip integration that is ideal for smaller, lighter and power-optimized wireless mobile devices.<\/span><\/p>\n<p>\n\tThis complete IC packaging design and analysis solution includes the Cadence OrbitIOTM Interconnect Designer, Cadence System-in-Package Layout, and Cadence Physical Verification System. They enable multi-substrate interconnect pathway design, refinement, implementation, and manufacturing verification and signoff spanning die I\/O pad rings through IC package to system PCB.<\/p>\n<p>\n\tThe new Cadence SiP Layout WLCSP option integrated with PVS provides generic silicon wafer-based packaging methodologies previously validated by TSMC for their Integrated Fan-Out (InFO) process. Enhancements to OrbitIO Interconnect Designer strengthen 2.5D interposer package design support, providing optimal multi-die, single-package interconnect integration. This enables higher performance for multi-substrate integrated devices with minimal size optimized for signal performance.<\/p>\n<p>\n\t<a href=\"http:\/\/www.cadence.com\/news\/ICpackaging172\">www.cadence.com\/news\/ICpackaging172<\/a>.<\/p>\n<p>\n\t&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Cadence Design Systems Inc., San Jose, Calif., offers a foundry-proven IC packaging design and analysis solution for advanced fan-out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs.<\/p>\n","protected":false},"author":63082,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[434,450,435,436,1],"tags":[],"class_list":["post-4166","post","type-post","status-publish","format-standard","hentry","category-electronics","category-general","category-news","category-news-articles","category-uncategorized"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.9 - 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