\n\tLasertec Corp., Japan, announces that it has launched its EZ300, a wafer edge inspection system based on a new concept that contributes to higher yields at wafer edges in the production of semiconductor chips.<\/p>\n
\n\tEZ300 is based on confocal optics, a Lasertec core technology, for inspection, review, and measurement of wafer edges. The EZ300 embodies an “All in One Concept” covering all in-line inspection needs up to root cause analysis for each defect type within a single platform.<\/p>\n
\n\tUntil today, it was considered a tough challenge to detect and identify defects of interest at wafer edges in production lines. EZ300 offers a solution with a combination of its high-resolution confocal optics and proprietary software algorithm, making it possible to perform automatic defect classification, including pit\/bump analysis and size measurement during inspection. This will enable users to establish in-line QC based on statistical process control, and to track down the cause of chip defects.<\/p>\n
\n\tHitherto-available wafer edge inspection tools require the use of SEM or AFM for defect classification and measurement. The conventional method is time-consuming and costly because defect position matching for multiple tools takes a long time. In contrast, EZ300 single-handedly offers 3D measurement of defects (width, height and roughness) based on its high-resolution reviews as well as defect classification based on image processing, thereby helping users achieve quick process feedback and optimization.<\/p>\n
\n\tThe scaling of integrated circuits has brought a significant increase in the number of transistors printed on a chip, achieving power saving, higher performance, and lower cost. However, further scaling will likely face various technical difficulties such as leak electricity. In this background, the industry is considering to improve yields at wafer edges in order to increase overall productivity in the existing manufacturing process. Furthermore, the introduction of 3D IC using through silicon via (TSV) and 3D memory chips with vertically formed transistors has brought new processes that make the quantitative management of wafer edges more important.<\/p>\n
\n\tEZ300 is a system that performs inspection, review, and measurement to address such customer needs. It is a versatile tool that meets the requirements of in-line quantitative management and process development analysis.<\/p>\n