{"id":4333,"date":"2015-03-14T15:07:22","date_gmt":"2015-03-14T15:07:22","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/23835743\/NEWS\/"},"modified":"2023-02-07T04:53:18","modified_gmt":"2023-02-07T04:53:18","slug":"system-on-a-chip-design-reduces-failure-rate-by-a-factor-of-nine","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/23835743\/NEWS\/","title":{"rendered":"System-on-a-chip design reduces failure rate by a factor of nine"},"content":{"rendered":"

\n\tChalmers University of Technology, Sweden, announces that the European Union’s DeSyRe project has resulted in a system-on-a-chip (SoC) that uses 48% less chip area and has a nine times lower failure rate. After three years of R&D, the DeSyRe (on-Demand System Reliability) chips have been shown to be even more reliable and to need even less power than predicted.<\/p>\n

\n\tThe Desyre consortium had initially promised new design techniques that would counter the increasing fault-rates expected for next-technology nodes, while at the same time they would reduce the power and performance penalties introduced by fault-tolerance measures. <\/p>\n

\n\tTo reach such ambitious goals, Desyre introduced a different, hybrid approach to reliability, which separates the system-on-chip into two different areas. One area comprises normal, interchangeable processing cores that are by nature susceptible to faults. The second area is extremely resistant to faults and monitors the sanity of the cores in the first area. It assures that each core in that area can handle an assigned sub-task correctly and efficiently, yet transfers tasks from one core to other idling cores in this same area in case of a diagnosed malfunction.<\/p>\n

\n\tAt the increasing fault-rates expected in the upcoming technology generations, DeSyRe will develop new design techniques for future SoCs, improving their reliability and reducing their power and performance overheads for fault-tolerance.<\/p>\n

\n\tDeSyRe will deliver a well-defined, generic, and repeatable design framework for a large variety of SoCs. The proposed framework will be applied to two medical SoCs with high reliability constraints and diverse performance and power requirements. The first is a portable artificial cerebellum used for rescuing part of a biological brain, while the second one is an implantable artificial pancreas which measures the glucose concentration in the blood of a diabetic person and accordingly releases the proper amount of insulin.<\/p>\n

\n\thttp:\/\/www.chalmers.se\/en\/news\/pressreleases\/Pages\/default.aspx<\/a><\/p>\n

\n\twww.desyre.eu<\/a><\/p>\n

\n\t <\/p>\n","protected":false},"excerpt":{"rendered":"

Chalmers University of Technology, Sweden, announces that the European Union’s DeSyRe project has resulted in a system-on-a-chip (SOC) that uses 48% less chip area and has a nine times lower failure rate.<\/p>\n","protected":false},"author":63082,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[434,450,438,435,436,1],"tags":[],"class_list":["post-4333","post","type-post","status-publish","format-standard","hentry","category-electronics","category-general","category-nanotechnology","category-news","category-news-articles","category-uncategorized"],"yoast_head":"\nSystem-on-a-chip design reduces failure rate by a factor of nine - Electronic Device Failure Analysis Society<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/23835743\/NEWS\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"System-on-a-chip design reduces failure rate by a factor of nine - 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