{"id":4405,"date":"2014-10-19T22:07:52","date_gmt":"2014-10-19T22:07:52","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/22564126\/NEWS\/"},"modified":"2023-02-07T04:53:24","modified_gmt":"2023-02-07T04:53:24","slug":"dcg-systems-meridian-probe-enables-full-wafer-diagnostic-and-testing-under-production-conditions","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/22564126\/NEWS\/","title":{"rendered":"DCG Systems Meridian probe enables full wafer diagnostic and testing under production conditions"},"content":{"rendered":"<p>DCG Systems Inc., Fremont, Calif., announces the first installation of the Meridian WS-DP (WaferScan Direct Probe) at Nvidia, a leading manufacturer of graphics processors for advanced visual computing. The Meridian WS-DP was selected for its ability to provide full wafer diagnostic and testing under production conditions, accelerating development and ramp of 16\/14nm and 10 nm technologies.<\/p>\n<p>With time-to-yield a key to profitability, advanced foundries, integrated device manufacturers, and fabless companies can no longer afford the limitations of conventional electrical fault analysis tools, which are only able to isolate critical electrical defects at the dicing and packaging stages. The Meridian WS-DP removes this limitation by providing optical electrical fault isolation (EFA) on full wafers using production testers, load boards, and probe cards, greatly accelerating time to defect localization. In addition, no modifications to wafer sort test programs are required, ensuring precise defect localization accuracy as well as faster workflow set-up between fabless manufacturers and their foundries.<\/p>\n<p>&#8220;The newly installed Meridian&nbsp;WS-DP uses a high bandwidth cable interface between the tester and the wafer probe card. Shmoo&nbsp;testing with and without the interface demonstrates excellent correlation after&nbsp;TDR&nbsp;recalibration,&#8221; said Howard Marks, Director of the Silicon Failure Analysis Lab at Nvidia.<\/p>\n<p>&#8220;This was a key requirement for us and helps ensure that we are targeting the same defect that was caught during production testing. In addition, the interface provides isolation of the high resolution optics in the&nbsp;WaferScan system from any vibrations that would otherwise come through from the tester. This allows us to achieve the&nbsp;<span style=\"font-family: Helvetica, Arial, sans-serif; font-size: 0.9375em; line-height: 1.333333333em;\">ultimate resolution that the optics are capable of.&#8221;<\/span><\/p>\n<p>&nbsp;<\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>DCG Systems Inc., Fremont, Calif., announces the first installation of the Meridian WS-DP (WaferScan Direct Probe) at Nvidia, a leading manufacturer of graphics processors for advanced visual computing.<\/p>\n","protected":false},"author":63082,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[434,450,438,435,436,1],"tags":[],"class_list":["post-4405","post","type-post","status-publish","format-standard","hentry","category-electronics","category-general","category-nanotechnology","category-news","category-news-articles","category-uncategorized"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.9 - 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