{"id":5432,"date":"2021-01-24T22:18:26","date_gmt":"2021-01-24T22:18:26","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/stanford-researchers-combine-processors-and-memory-on-multiple-hybrid-chips-to-run-ai-on-battery-powered-smart-devices\/"},"modified":"2023-02-23T21:25:27","modified_gmt":"2023-02-23T21:25:27","slug":"stanford-researchers-combine-processors-and-memory-on-multiple-hybrid-chips-to-run-ai-on-battery-powered-smart-devices","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/43266310\/NEWS\/","title":{"rendered":"Stanford researchers combine processors and memory on multiple hybrid chips to run AI on battery-powered smart devices"},"content":{"rendered":"

A team at Stanford University, Palo Alto, Calif., including computer scientist Mary Wootters and electrical engineer H.-S. Philip Wong has designed a system that can run AI tasks faster and with less energy by harnessing eight hybrid chips, each with its own data processor built right next to its own memory storage.<\/p>\n

Smart watches and other battery-powered electronics would be even smarter if they could run AI algorithms. But efforts to build AI-capable chips for mobile devices have so far hit a wall. In traditional electronics, separate chips process and store data, wasting energy as they toss data back and forth over  a so-called \u201cmemory wall\u201d that separates data processing and memory chips but must work together to meet the massive and continually growing computational demands imposed by AI. The team\u2019s new algorithms combine several energy-efficient hybrid chips to create the illusion of one mega\u2013AI chip.<\/p>\n

\u201cTransactions between processors and memory can consume 95 percent of the energy needed to do machine learning and AI, and that severely limits battery life,\u201d said computer scientist Subhasish Mitra, senior author of a new study published in Nature Electronics.<\/p>\n

\u201cIf we could have built one massive, conventional chip with all the processing and memory needed, we\u2019d have done so, but the amount of data it takes to solve AI problems makes that a dream,\u201d Mitra said. \u201cInstead, we trick the hybrids into thinking they\u2019re one chip, which is why we call this the Illusion System.\u201d<\/p>\n

The work builds on the team\u2019s development of a new memory technology, RRAM, that stores data even when power is switched off \u2013 like flash memory \u2013 only faster and more energy efficiently. Their latest design incorporates a critical new element: algorithms that meld its eight, separate hybrid chips into one energy-efficient AI-processing engine.<\/p>\n

The Stanford-led team built and tested its prototype with help from collaborators at the French research institute CEA-Leti and at Nanyang Technological University in Singapore. The team\u2019s eight-chip system is just the beginning. In simulations, the researchers showed how systems with 64 hybrid chips could run AI applications seven times faster than current processors, using one-seventh as much energy.<\/p>\n

The team also developed new algorithms to recompile existing AI programs, written for today\u2019s processors, to run on the new multi-chip systems. Collaborators from Facebook helped test AI programs that validated their efforts. Next steps include increasing the processing and memory capabilities of individual hybrid chips and demonstrating how to mass produce them cheaply.<\/p>\n

The researchers developed Illusion as part of the Electronics Resurgence Initiative (ERI), a $1.5 billion program sponsored by the Defense Advanced Research Projects Agency. Wong believes Illusion Systems could be ready for marketability within three to five years.<\/p>\n

 <\/p>\n

For more information:<\/p>\n

Stanford University
\nhttps:\/\/www.uah.edu\/<\/a><\/p>\n

CEA-Leti
\nhttps:\/\/www.leti-cea.com<\/a><\/p>\n

Nanyang Technological University
\nhttps:\/\/www.ntu.edu.sg<\/a><\/p>\n

Image \u2013 Hardware and software innovations give eight chips the illusion that they\u2019re one mega-chip working together to run AI. Courtesy of Stocksy \/ Drea Sullivan.<\/em><\/p>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

A team at Stanford University, Palo Alto, Calif., has designed a system that can run AI tasks faster and with less energy by harnessing eight hybrid chips, each with its own data processor built right next to its own memory storage.<\/p>\n","protected":false},"author":63103,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[446,434,435,436,1],"tags":[],"class_list":["post-5432","post","type-post","status-publish","format-standard","hentry","category-consumer-products","category-electronics","category-news","category-news-articles","category-uncategorized"],"yoast_head":"\nStanford researchers combine processors and memory on multiple hybrid chips to run AI on battery-powered smart devices - Electronic Device Failure Analysis Society<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/43266310\/NEWS\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Stanford researchers combine processors and memory on multiple hybrid chips to run AI on battery-powered smart devices - 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