{"id":5674,"date":"2018-02-24T11:44:52","date_gmt":"2018-02-24T11:44:52","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/cadence-and-advanced-semiconductor-develop-sip-eda-solution-for-multi-die-packages\/"},"modified":"2023-02-23T21:26:59","modified_gmt":"2023-02-23T21:26:59","slug":"cadence-and-advanced-semiconductor-develop-sip-eda-solution-for-multi-die-packages","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/33165224\/NEWS\/","title":{"rendered":"Cadence and Advanced Semiconductor develop SIP-EDA solution for multi-die packages"},"content":{"rendered":"<p><span><span>Advanced Semiconductor Engineering Inc., Taiwan, and Cadence Design Systems Inc., San Jose, Calif., announce that they have collaborated to release a System-in-Package (SiP) EDA solution that addresses the challenges of designing and verifying Fan-Out Chip-on-substrate multi-die packages. <\/span><\/span><\/p>\n<p><span><span>The solution consists of the SiP-id (System-in-Package &#8211; intelligent design) design kit, an enhanced reference flow including IC packaging and verification tools from Cadence, and a new methodology that aggregates the requirements of wafer-, package-, and system-level design into a unified and automated flow. By deploying the SiP-id methodology, designers can reduce design iterations and greatly improve throughput as compared to existing advanced packaging EDA tools, reducing the time needed to design and verify ultra-complex SiP packages.<\/span><\/span><\/p>\n<p><span><span>Previously, IC packaging engineers leveraged standard EDA design tools coupled with a set of loosely defined rules to lay out their packages. However, this approach has many limitations when designing today\u2019s advanced multi-die packages. To provide a more holistic approach to the design and verification of SiP and advanced fan- out packages, ASE and Cadence collaborated closely to develop a design kit, methodology, and streamlined and automated reference flow using enhanced Cadence\u00ae IC packaging and verification tools, all tailored for ASE\u2019s advanced IC package technologies. In a typical use case with high-pin-count dies, packaging engineers using SiP-id and the accompanying reference flow and methodology were able to reduce time from more than six hours to only 17 minutes, compared to existing tools with manual operation.<\/span><\/span><\/p>\n<p><span><a href=\"http:\/\/www.aseglobal.com\/en\/Technology\/AdvancedTechnology.asp\"><span>www.aseglobal.com\/en\/Technology\/AdvancedTechnology.asp<\/span><\/a> <\/span><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Advanced Semiconductor Engineering Inc., Taiwan, and Cadence Design Systems Inc., San Jose, Calif., announce that they have collaborated to release a System-in-Package (SiP) EDA solution that addresses the challenges of designing and verifying Fan-Out Chip-on-substrate multi-die packages.<\/p>\n","protected":false},"author":63103,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[434,435,436,1],"tags":[],"class_list":["post-5674","post","type-post","status-publish","format-standard","hentry","category-electronics","category-news","category-news-articles","category-uncategorized"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.9 - 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