{"id":6073,"date":"2018-03-19T10:31:56","date_gmt":"2018-03-19T10:31:56","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/imec-and-cadence-tape-out-industry-s-first-3nm-test-chip-to-advance-next-gen-design\/"},"modified":"2023-02-23T21:29:35","modified_gmt":"2023-02-23T21:29:35","slug":"imec-and-cadence-tape-out-industry-s-first-3nm-test-chip-to-advance-next-gen-design","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/33311975\/NEWS\/","title":{"rendered":"Imec and Cadence tape out industry\u2019s first 3nm test chip to advance next-gen design"},"content":{"rendered":"

Imec, Belgium, and Cadence Design Systems Inc., San Jose, Calif., announce that their long-standing collaboration has resulted in the industry\u2019s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence Innovus Implementation System and Genus Synthesis Solution. <\/span><\/span><\/p>\n

Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and Imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.<\/span><\/span><\/p>\n

The Cadence Innovus Implementation System is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance and area (PPA) targets while accelerating time to market. <\/span><\/span><\/p>\n

The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10X. <\/span><\/span><\/p>\n

www.cadence.com\/go\/innovus3nm<\/span><\/a>, <\/span>www.cadence.com\/go\/genus3nm<\/span><\/a>.<\/span><\/span><\/p>\n

For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions. <\/span><\/span><\/p>\n

For more information on EUV technology and 193i technology, visit <\/span>https:\/\/www.imec-int.com\/en\/articles\/imec-presents-patterning-solutions-for-n5-equivalent-metal-layers<\/span><\/a>.<\/span><\/span><\/p>\n","protected":false},"excerpt":{"rendered":"

Imec, Belgium, and Cadence Design Systems Inc., San Jose, Calif., announce that their long-standing collaboration has resulted in the industry\u2019s first 3nm test chip tapeout.<\/p>\n","protected":false},"author":63103,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[434,435,436,1],"tags":[],"class_list":["post-6073","post","type-post","status-publish","format-standard","hentry","category-electronics","category-news","category-news-articles","category-uncategorized"],"yoast_head":"\nImec and Cadence tape out industry\u2019s first 3nm test chip to advance next-gen design - Electronic Device Failure Analysis Society<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/33311975\/NEWS\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Imec and Cadence tape out industry\u2019s first 3nm test chip to advance next-gen design - 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