Cadence, Santa Clara, Calif., rolled out Verisium, its latest AI-powered electronic design automation (EDA) platform which promises to ease the amount of time and resources that chipmakers put into the verification process.<\/p>\n
MediaTek and Samsung are among the first companies using Verisium to identify bugs in system-on-chip (SoC) designs and diagnose what\u2019s causing things to go wrong.<\/p>\n
Verisium is a complement to its Cerebrus Intelligent Chip Explorer platform for AI-enhanced implementation and Optimality Intelligent System Explorer for AI-powered system-level analysis.<\/p>\n
The purpose of verification is to identify and resolve chip design defects in a pre-manufactured state. It\u2019s the end-stage process of testing the quality of the design and that everything inside works as planned in a product.<\/p>\n
The verification process usually starts after you complete the chip design. The hardware is simulated with software code in a hardware description language (HDL) used to test the various building blocks of the SoC. The test bench effectively creates a virtual version of the SoC that can be supplied with signals. Subsequently, you can measure and evaluate the responses from the SoC to figure out whether the SoC or IP inside has any issues.<\/p>\n
Verisium works with Cadence\u2019s existing verification engines: Palladium for emulation, Protium for prototyping, Xcelium for simulation, Jasper for formal verification, and its Helium virtual and hybrid studios.<\/p>\n
Previously, you would have to run every one of these engines separately for every step in the verification process\u2014what Cadence calls \u201ca single-run, single-engine\u201d approach. Verisium, on the other hand, leverages big data and AI to optimize multiple runs of multiple engines over the full SoC design and verification campaign.<\/p>\n
As SoC complexity continues to rise, the verification process tends to take more time and resources than any other silicon engineering task. And so, as Cadence tells it, verification is ripe for improvement using AI.<\/p>\n
Verisium also runs on top of Cadence\u2019s new \u201cJedAI\u201d platform, which pools vast quantities of data stemming from the chip design process, analyzes it to identify areas of improvement, and even stores it for future use.<\/p>\n
JedAI is a platform in the sense that its AI-powered offerings\u2014Verisium, Cerebrus, and Optimality\u2014and third-party silicon lifecycle management systems sit on top of it. When it comes to using Verisium, its verification tools feed data stemming from the verification process, ranging from waveforms, coverage, and reports to log files, into the JedAI platform, where it\u2019s all stored and evaluated.<\/p>\n
JedAI builds machine-learning models and mines other proprietary metrics from the data, sharing what it learns with the company\u2019s Verisium to identify potential areas of improvement or root-cause issues.<\/p>\n
Paul Cunningham, senior vice president and general manager of Cadence\u2019s system and verification division, said Verisium would help chip companies make more informed decisions during the design and verification process. But the biggest impact is apparently on the productivity side of things.<\/p>\n
The company said its customers are already using Verisium to triage failing tests more than 3X faster than they could previously, with reductions in the time it takes to determine the root-cause failure by up to 75%.
\nGiven that failure analysis and debug represent 50% (or in some cases more) of the time chip firms devote on verification, Cadence claimed the AI-driven Verisium tool could result in major improvements in productivity.<\/p>\n
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For more information:<\/p>\n
Cadence<\/p>\n