{"id":6195,"date":"2020-07-18T21:24:24","date_gmt":"2020-07-18T21:24:24","guid":{"rendered":"https:\/\/staging.asminternational.org\/edfas\/imec-and-global-foundries-demonstrate-chip-optimized-for-calculations-in-memory-devices\/"},"modified":"2023-02-23T21:30:21","modified_gmt":"2023-02-23T21:30:21","slug":"imec-and-global-foundries-demonstrate-chip-optimized-for-calculations-in-memory-devices","status":"publish","type":"post","link":"https:\/\/www.asminternational.org\/edfas\/results\/-\/journal_content\/56\/10192\/41410632\/NEWS\/","title":{"rendered":"Imec and Global Foundries demonstrate chip optimized for calculations in memory devices"},"content":{"rendered":"<p>Imec, Belgium, and Global Foundries, Santa Clara, Calif., announce a hardware demonstration of a new artificial intelligence chip. Based on Imec\u2019s analog-in-memory computing (AiMC) architecture utilizing GF\u2019s 22FDX solution, the new chip is optimized to perform deep neural network calculations on in-memory computing hardware in the analog domain.&nbsp;<\/p>\n<p>Achieving record-high energy efficiency up to 2900 TOPS\/W, the accelerator is a key enabler for inference-on-the-edge for low-power devices. The privacy, security, and latency benefits of this new technology will have an impact on AI applications in a wide range of edge devices, from smart speakers to self-driving vehicles.<\/p>\n<p>Since the early days of the digital computer age, the processor has been separated from the memory. Operations performed using a large amount of data require a similarly large number of data elements to be retrieved from the memory storage. This limitation, known as the von Neumann bottleneck, can overshadow the actual computing time, especially in neural networks \u2013 which depend on large vector matrix multiplications. These computations are performed with the precision of a digital computer and require a significant amount of energy. However, neural networks can also achieve accurate results if the vector-matrix multiplications are performed with a lower precision on analog technology.<\/p>\n<p>To address this challenge, Imec and its industrial partners in Imec\u2019s industrial affiliation machine learning program, including GF, developed a new architecture which eliminates the von Neumann bottleneck by performing analog computation in SRAM cells.&nbsp;<\/p>\n<p>The resulting Analog Inference Accelerator (AnIA), built on GF\u2019s 22FDX semiconductor platform, has exceptional energy efficiency. Characterization tests demonstrate power efficiency peaking at 2,900 tera operations per second per watt (TOPS\/W). Pattern recognition in tiny sensors and low-power edge devices, which is typically powered by machine learning in data centers, can now be performed locally on this power-efficient accelerator.&nbsp;<\/p>\n<p>www.globalfoundries.com&nbsp;<br \/>\n&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Imec, Belgium, and Global Foundries, Santa Clara, Calif., announce a hardware demonstration of a new artificial intelligence chip.<\/p>\n","protected":false},"author":63103,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[434,437,438,435,436,1],"tags":[],"class_list":["post-6195","post","type-post","status-publish","format-standard","hentry","category-electronics","category-materials-testing-and-evaluation","category-nanotechnology","category-news","category-news-articles","category-uncategorized"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.9 - 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