Intel Corp., Santa Clara, Calif., devised a process to manufacture, test, and demonstrate positive performance results with its new backside power solution called PowerVia, enabling chipmaking to go two-sided for the first time.<\/p>\n
This new approach to delivering power required a radical rethink to both how chips are made and how they are tested. Typically microchips are built from the bottom up, in layers, including wires among the top layers that bring in the power that makes the chip go. When the chip is done, they are flipped over and are enclosed in packaging that provides connections to the outer world.<\/p>\n
Unfortunately, this approach is running into problems. As they get smaller and denser, the layers that share interconnects and power connections have become an increasingly chaotic web that hinders the overall performance of each chip. Power and signals fade, requiring workarounds or simply dumping more power in.<\/p>\n
Research and development on the backside power solution that Intel and leading-edge chipmakers are all working toward dates back a decade. This approach moves the power wires below the transistor to the back side of the chip leaving the front side cleanly focused only on interconnection.<\/p>\n
Ben Sell, vice president of technology development at Intel and part of the team that brought PowerVia to fruition, explains how it works. Transistors are built first, as before, with the interconnect layers added next. Now the fun part: flip over the wafer and \u201cpolish everything off,\u201d Sell notes, to expose the bottom layer to which the metal layers for power will be connected. \u201cWe call it silicon technology,\u201d he adds, \u201cbut the amount of silicon that\u2019s left on these wafers is really tiny.\u201d<\/p>\n
After the polish, \u201cnow you only have very few metal layers and they\u2019re all very thick,\u201d Sell explains \u2014 remember he lives in the land of nanometers, so \u201cthick\u201d means mere micrometers. That leaves \u201ca very direct path for the power delivery to your transistor.\u201d<\/p>\n
The benefits of this approach are manifold, Sell confirms, surpassing the added complexity of the new process.<\/p>\n
The wires for power, for example, can take up to 20% of that front-side real estate, so with them gone, the interconnect layers can be \u201crelaxed.\u201d \u201cThat more than offsets the cost of this whole big process,\u201d Sell notes, simplifying what had been the most tortuous portion of the manufacturing flow. The net effect is that the two-part flip-it-over process is actually cheaper than the old way.<\/p>\n
The benefits aren\u2019t limited to manufacturing. The test chip the Intel team used to prove out the approach \u2014 called Blue Sky Creek and based on the Efficient-core (E-core) coming in Intel\u2019s forthcoming Meteor Lake processor for PCs \u2014 demonstrated that PowerVia solved both problems caused by the old method. With separated and fatter wires for power and interconnection, \u201cyou get better power delivery and you get better signal wiring,\u201d says Sell.<\/p>\n
For your average computer user, this means more efficient speed. Get work done faster and with less power, the promise of Moore\u2019s Law delivered again. The Intel E-core designed with PowerVia demonstrates >5% frequency improvement and >90% cell density with acceptable debug times as Intel 4. Sell confirms this is a \u201csubstantial\u201d frequency boost for just moving wires around.<\/p>\n
Today, chip-testing techniques are based on the accessibility of the transistors in that first and lowest layer. With the transistors now sandwiched in the middle of the chip, \u201ca lot of those techniques had to be redeveloped,\u201d says Sell.<\/p>\n
\u201cAcceptable debug times\u201d \u2014 is a critical achievement alongside the product improvements. \u201cWe have made tremendous progress over the last couple of years in developing those debug capabilities and proving them on Blue Sky Creek,\u201d Sell asserts.<\/p>\n
Intel doesn\u2019t usually make test chips as functional and complete as Blue Sky Creek. In this case, the teams needed to verify not only that they could build and test a chip this way, but also that the new configuration wouldn\u2019t bring new issues into the final product.<\/p>\n
For instance, heat. \u201cNormally you use the silicon side also for heat dissipation,\u201d Sell explains. \u201cSo now you have sandwiched your transistors and the question is, \u2018Do we have a thermal problem? Do we get a lot of local heating?\u2019\u201d At this point you can probably guess the answer: no.<\/p>\n
\u201cWhat was most amazing,\u201d Sell recalls, \u201cwas despite these radical changes\u201d \u2014 sandwiching transistors in the middle of the chip and introducing this heavy \u201cpolishing\u201d to the process \u2014 \u201cwe could make the transistors look very, very close to what we had in Intel 4.\u201d<\/p>\n
The first opportunity to feel the many benefits of PowerVia will come in 2024 in the form of Arrow Lake, a next-generation Intel processor for PCs built using the Intel 20A process. Its billions of transistors will be inverted, working more efficiently than ever.<\/p>\n
<\/p>\n
******************************************************************************************<\/p>\n