Sample Preparation User Group<\/strong><\/h5>\n\nOptical Fault Isolation\/Test and Diagnostics User Group<\/h5>\n\nIntegrated PFA User Group<\/h5>\n\nSystem in Package User Group<\/h5>\n\nFocused Ion Beam User Group<\/h5>\n\n
Wednesday, October 7, 2026: 10:20 - 11:20 AM<\/strong><\/p>\n\nTuesday, October 6, 2026: 1:50 - 2:50 PM<\/strong><\/p>\n\nMonday, October 5, 2026: 4:00 - 5:00 PM<\/strong><\/p>\n\nMonday, October 5, 2026: 4:00 - 5:00 PM<\/strong><\/p>\n\nMonday, October 5, 2026: 4:00 - 5:00 PM<\/strong><\/p>\n\nTuesday, October 6, 2026: 12:50 - 1:50 PM<\/strong><\/p>\n\nNanoprobing\/SPM User Group<\/h5>\n\n
Tuesday, October 6, 2026: 4:00 - 5:00 PM<\/strong><\/p>\n\nModerators:<\/span><\/b>\u00a0
Dan Bockelman, Intel Corporation<\/span>\u00a0
Dan Bodoh, NXP Semiconductors<\/span>\u00a0
Munindhran Rao, Cirrus Logic<\/span>
<\/span>Arun Karunanithi, AMD<\/span>\u00a0
<\/span>The Optical Fault Isolation, Test, and Diagnosis User Group will include discussions on a variety of topics related to optical probing techniques for fault isolation as well as test and diagnosis.<\/span>\u00a0<\/span>The format will be open discussion with opportunities for audience participation.<\/span>\u00a0<\/span><\/p>Examples of discussion topics include:<\/span>\u00a0<\/span><\/i>\u00a0<\/span><\/p>- Improvements in Diagnosis<\/span>\u00a0<\/span><\/li><\/ul>
- LIT Techniques<\/span>\u00a0<\/span><\/li><\/ul>
- Laser-based Techniques<\/span>\u00a0<\/span><\/li><\/ul>
- Techniques for Backside Power Delivery FI<\/span>\u00a0<\/span><\/li><\/ul>
- Impact of AI in Optical FI and Diagnosis<\/span>\u00a0<\/span><\/li><\/ul>\n\n
Moderators:<\/span><\/b>\u00a0
Hemachandar\u00a0\u201cChandu\u201d\u00a0Tanukonda, Intel Corporation<\/span>\u00a0
Jer O\u2019Sullivan, Analog Devices<\/span>\u00a0
Bernice Zee, AMD<\/span>
<\/span>As advanced packaging technologies continue to evolve, System in Package (SiP) architectures are enabling unprecedented levels of heterogeneous integration, performance, and functionality. However, the increasing complexity of chiplet-based systems, high-bandwidth memory integration, advanced interconnects, and large-form-factor packages is creating new challenges for failure analysis and debug. In support of this year's ISTFA theme, \"Design for Analysis,\" this user group will explore emerging gaps, industry pain points, and innovative approaches that are shaping the future of analysis and characterization of advanced SiP products. Through invited talks and interactive audience discussions, participants will have the opportunity to share experiences, discuss solutions, and identify future needs for the FA community.\u00a0
<\/span>As the semiconductor industry continues to adopt increasingly complex packaging architectures, traditional failure analysis workflows are being challenged by reduced physical access, higher device integration, greater power densities, and shrinking interconnect dimensions. New package architectures often combine multiple dies, process technologies, memory stacks, and specialized accelerators within a single package, creating\u00a0additional\u00a0layers of complexity for root-cause identification and fault localization. These developments are\u00a0driving the need for new methodologies, improved design-for-analysis strategies, and enhanced collaboration between design, manufacturing, reliability, test, and failure analysis teams.<\/span>
<\/span>This session will feature invited presentations and audience-driven discussions focused on practical challenges and emerging solutions in the analysis of advanced packaging technologies. Particular emphasis will be placed on non-destructive inspection techniques, acoustic imaging, 3DXRAY imaging, and the unique challenges associated with high-power and AI-driven products. Attendees will also have the opportunity to participate in live polling and open discussions to exchange ideas, benchmark industry practices, and identify key technology gaps that may influence future tool development and analysis methodologies.\u00a0
<\/span>Whether your organization is developing, manufacturing, or analyzing advanced packaging solutions, this session provides a forum to discuss\u00a0common challenges, share lessons learned, and explore future directions for\u00a0SiP\u00a0failure analysis and characterization.<\/span>
<\/span>Topics for the System in Package User Group, ISTFA 2026 include:<\/span>\u00a0<\/span><\/p>- State of\u00a0SiP\u00a0Landscape<\/span>\u00a0<\/span><\/li><\/ul>
- Emerging Failure Analysis Challenges Not Yet Solved<\/span>\u00a0<\/span><\/li><\/ul>
- Design for Analysis in Advanced Packaging<\/span>\u00a0<\/span><\/li><\/ul>
- Acoustic Imaging (CSAM) Challenges and Opportunities<\/span>\u00a0<\/span><\/li><\/ul>
- 3D X-ray and Non-Destructive Imaging Advances<\/span>\u00a0<\/span><\/li><\/ul>
- High-Power Product Failure Analysis<\/span>\u00a0<\/span><\/li><\/ul>
- Future Direction for\u00a0SiP<\/span>\u00a0<\/span><\/li><\/ul>\n\n
Moderators:\u202f<\/span><\/b>\u00a0
Valerie Brogden, Covalent Metrology<\/span>\u00a0
<\/span>Steven Herschbein, Independent Consultant<\/span>\u00a0
Edward Principe, Synchrotron Research<\/span>\u00a0
Michael Wong,\u00a0Thermo\u00a0Fisher Scientific<\/span>\u00a0<\/span><\/p>Focused Ion Beam (FIB) technology is evolving rapidly\u2014are you keeping up?<\/span>\u00a0<\/span><\/p>Modern FIB platforms are essential for failure analysis, semiconductor manufacturing, and research, enabling everything from cross-sectioning and high-resolution imaging to\u00a0TEM\u00a0sample preparation and circuit edit. New ion species, process gases, automation, and accessories continue to expand\u00a0what's\u00a0possible while raising new questions about tool ownership, outsourcing, service models, and emerging device architectures.<\/span>\u00a0<\/span><\/p>Join the FIB community for this interactive 90-minute ISTFA session. Through a series of lightning talks and an open discussion,\u00a0we'll\u00a0share real-world challenges, troubleshooting tips, and future directions for FIB technology.<\/span>\u00a0<\/span><\/p>Whether\u00a0you're\u00a0a lab manager, tool operator, experienced user, or simply FIB-curious, everyone is welcome. Bring your questions, experiences, and\u00a0ideas\u2014this session is driven by the community, and your perspective matters.<\/span>\u00a0<\/span><\/p>\n\nModerators:\u00a0<\/strong>
Konstantin Schekotihin, University Klagenfurt<\/span>\u00a0
<\/span>Florian Felux, Infineon Technologies<\/span>\u00a0
<\/span>Peter Hoffrogge, PVA\u00a0Tepla<\/span>\u00a0
Christoph Maaier, Infineon Technologies<\/span>\u00a0
Michael Beetz, Infineon Technologies<\/span>\u00a0
\u00a0<\/span><\/p>AI in FA is growing far beyond finding defects in microscope images. Today, new software automatically plans electrical testing to isolate faults, analyzes test equipment log files, and performs temperature or stress mapping. Large language models serve as the \"brains\" of new smart assistants (agents) that can understand engineering instructions, plan complex workflows, and automatically run various lab tools, such as image search programs and database systems, to organize the entire diagnostic process. To support these capabilities, the AI User Group (AI UG) focuses on three areas of intelligence that enable these agents to work:<\/span><\/p>- Ontology Definition: The rules and dictionaries agents use to understand instructions and plan diagnostic steps.<\/span>\u00a0<\/span><\/li><\/ul>
- Data-Driven Pattern Learning: The software tools and ML models that agents can run to find defects in images, measurements, and logs.<\/span>\u00a0<\/span><\/li><\/ul>
- Combined Reasoning: How agents connect these tools to engineering databases to explain the root cause of a failure.<\/span>\u00a0
\u00a0<\/span><\/li><\/ul>However, daily lab operations face major challenges: scattered, uncleaned vendor data, a lack of data management (tracking origins and protecting design security), and difficulties connecting older tools.
<\/span>The AI UG is bridging this gap through key standardization and cleanup initiatives:<\/span><\/p>- \u00a0Common Engineering Language (FA Ontology): We support the EU-driven effort (FA2IR\/FA4.0 projects) to build a unified failure dictionary. This acts as a standard directory of failure causes\u00a0that different\u00a0lab tools\u00a0can read.<\/span>\u00a0<\/span><\/li><\/ol>
- SEMI Standardized Text Format: We promote a standardized text format (JSON) that attaches description tags to images and logs. This lets legacy equipment and automated systems process data automatically without manual reformatting.<\/span>\u00a0<\/span><\/li><\/ol>
- Data Cleanup & Management: We\u00a0establish\u00a0simple guidelines for cleaning, labeling, and organizing records to prepare them for AI training while keeping sensitive design data safe.<\/span>\u00a0<\/span><\/li><\/ol>
- Tool Integration: We connect these assistants with databases and software platforms to automate routine testing.<\/span>\u00a0<\/span><\/li><\/ol>\n\n
Moderators:<\/span><\/b>\u00a0<\/span><\/p>Scott P. Lockledge, Ph.D.,\u00a0Tiptek\u00a0LLC<\/span>
<\/span>Tad Daniels,\u00a0Thermo\u00a0Fisher Scientific<\/span>
<\/span>Ricky Anthony, Analog Devices<\/span>\u00a0<\/span><\/p>This year\u2019s session highlights scanning probe microscopy (SPM) technique and is entitled\u00a0<\/span>\u201c<\/span>Scanning Probe Microscopy Electrical Techniques and Advanced Nanoprobing: The Importance of Sample Preparation\u201d.<\/span><\/i>\u00a0SPM electrical characterization is important for advanced node semiconductor characterization and increasingly depends upon careful and proper preparation of samples to obtain useful results.\u00a0\u00a0For example, PFIB\u2019s are often replacing traditional planar polishing to ensure precise planar delayering. These PFIB sample preparation methods enable SPM probes to make\u00a0accurate\u00a0and low resistance contacts for electrical characterization techniques.<\/span>\u00a0<\/span><\/p>\n\nModerators:<\/span><\/b>\u00a0
Pawel Nowakowski,\u00a0Fischione\u00a0Instruments<\/span>\u00a0
Craig Nakakura, Sandia National Laboratory<\/span>
<\/span>Rosine Coq Germanicus, UNICAEN<\/span>
As semiconductor technologies continue to evolve, physical failure analysis has become increasingly dependent on integrating multiple analytical techniques rather than relying on a single method.\u00a0Identifying\u00a0the root cause of a failure now requires not only the right analytical tools, but also the right analytical strategy.<\/span>\u00a0<\/span><\/p>Join us for an interactive discussion focused on the integration of electrical characterization, de-processing, imaging, materials analysis, and nanoscale characterization into efficient and effective failure analysis workflows. Through short presentations and open discussion, participants will share challenging cases, discuss workflow bottlenecks, and exchange practical experiences that help transform electrical anomalies into definitive physical root causes.<\/span>\u00a0<\/span><\/p>Discussion Topics:<\/span>\u00a0<\/span><\/p>- Workflow Optimization \u2013 Developing decision-making strategies that improve efficiency, reduce analysis time, and maximize the likelihood of success, includingidentifyingthe essential analytical techniques and when they provide the greatest value.<\/span>\u00a0<\/span><\/li>
- From Electrical Failure to Physical Root Cause \u2013 How do we choose the most effective analytical path while minimizing unnecessary sample preparation and analysis?<\/span><\/li>
- Cross-Correlated Analysis \u2013 Integrating electrical characterization, imaging, de-processing, microscopy, spectroscopy, and nanoscale techniques to build confidence in root cause identification.<\/span><\/li>
- Workflow Optimization \u2013 Developing decision-making strategies that improve efficiency, reduce analysis time, and maximize the likelihood of success.<\/span><\/li>
- Advanced Packaging Challenges \u2013 Addressing analytical complexities associated with chiplets, 2.5D\/3D integration, hybrid bonding, backside power delivery, and heterogeneous integration.<\/span><\/li>
- Lessons Learned \u2013 Open discussion of difficult cases, unexpected obstacles, and practical solutions from the failure analysis community.<\/span><\/li><\/ul>
Whether you work in failure analysis, process integration, analytical microscopy, or materials characterization, this User Group\u00a0provides\u00a0an opportunity to exchange ideas, discuss real-world challenges, and help define best practices for integrated physical failure analysis in next-generation semiconductor technologies.<\/span>\u00a0<\/span><\/p>\n\nModerators:<\/span><\/b>\u00a0
Jim Colvin, FA Instruments, Inc.<\/span>
<\/span>Chris Richardson, Allied High Tech<\/span>
<\/span>Rosalinda Ring, Neno Vision<\/span>\u00a0
Bryan Tracy,\u00a0ibss\u00a0Group<\/span>\u00a0
Nathan Bakken, Intel<\/span>\u00a0
<\/span>As technologies push device complexity to its limits, the demand for high-quality, defect-free sample preparation has never been more critical. Breakthroughs like backside power delivery networks (BPDN) and 3D heterogeneous integration offer massive performance gains but they also block traditional physical and optical diagnostic paths. To survive this shift, the industry must transition from reactive troubleshooting to Design for Failure Analysis (DFA). We can no longer treat sample preparation as an afterthought; we must design devices so they can actually be prepared and analyzed.<\/span>\u00a0<\/span><\/p>Our failure analysis lab\u2019s sample preparation capabilities are hitting a physical wall with modern device architectures. Delayering advanced nodes now means handling fragile materials, ultra-thin layers, and delicate nanoscale features without causing structural collapse, while BPDN buries active silicon beneath complex metal networks. This forces us to adapt our mechanical and plasma\u00a0deprocessing\u00a0workflows for the die's most complex side. At the same time, we must achieve uniform, artifact-free silicide removal on legacy devices, and map localized strain across dense packaging interfaces. Overcoming these hurdles requires a dual approach: advancing our physical\u00a0deprocessing\u00a0while actively using DFA principles to ensure these complex structures can survive the prep process.\u00a0<\/span>\u00a0<\/span><\/p>Join our Sample Preparation User Group for an interactive discussion on the next wave of sample prep workflows, DFA-driven layouts, and localized strain-measurement techniques. This is your forum to share practical insights, troubleshoot tricky lab prep work, and explore\u00a0what\u2019s\u00a0next.<\/span>\u00a0<\/span><\/p>The Sample Prep User Group Mission<\/span><\/i>: If a device cannot be prepared, it cannot be analyzed. By bridging the gap between chip design and the prep lab, we ensure the diagnostics of tomorrow remain possible.<\/span><\/i>\u00a0<\/span><\/p>Don\u2019t\u00a0miss this opportunity to connect with fellow sample prep engineers, lab managers, and DFA advocates. Bring your toughest sample prep hurdles, share your custom lab recipes, and leave with practical solutions to your daily\u00a0deprocessing\u00a0challenges.<\/span>\u00a0<\/span><\/p>","protected":false},"excerpt":{"rendered":"","protected":false},"author":63081,"featured_media":0,"parent":443,"menu_order":5,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-2312","page","type-page","status-publish","hentry"],"bricks_content":"User Groups<\/h1>\n\n
The ISTFA 2026 User Group Sessions<\/strong> offer an engaging platform for professionals to discuss and share insights on the latest trends in failure analysis. Covering seven distinct areas, these interactive sessions immerse attendees in a collaborative environment focused on innovation and knowledge sharing. It is an ideal opportunity for participants to enhance their\u00a0<\/span>expertise<\/span>
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