Cadence Design Systems Inc., San Jose, Calif., and Applied Materials Inc., Santa Clara, Calif., are collaborating on a development program to optimize the chemical-mechanical planarization (CMP) process through silicon characterization and modeling for advanced-node designs at 14 nm and below.
Oxford Instruments launches EBSD detector with speed of 1580 points per second
National Instruments Semiconductor Test Systems feature PXI modular instrumentation
This town has been on fire for 50 years
Could black phosphorus be the next silicon?
New material could make it possible to pack more transistors on a chip, research suggests.





