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The Power of Semiconductor Memory Failure Signature Analysis

Author: Cary A. Gloor, LSI Logic Corporation   |   Document Download   |   Product code: ZMEFA2011P239

File size: 760 KB

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It has long been recognized that semiconductor memories are superb drivers for process yield and reliability improvement because of their highly structured architecture and use of aggressive layout rules. [1] This combination provides outstanding failure signature analysis possibilities for the entire design, manufacturing, and test process. This includes areas of study such as design and layout robustness, baseline yield analysis, maverick lot analysis, process and product reliability qualification, lot acceptance testing, and customer return failure analysis (FA). These areas of study are important whether the memories are stand-alone devices or deeply embedded within an Application Specific Integrated Circuit (ASIC).
  • From: Microelectronics Failure Analysis, Desk Reference Sixth Edition
  • Published: October 01, 2011
  • Pages: 7
  • Review Type: Peer reviewed