Engineers from Global Foundries and Mentor presented a discussion of “Automated Multi-level Circuit Net Trace for Hotspot Analysis” at the ASM International ISTFA 2019 conference in Portland, Oregon.
Post-fault isolation layout net trace and circuit analysis based on abnormal hotspots is a critical step because it directly impacts the outcome of failure analysis. In this work, we review current commercial net tracing solutions in terms of their strengths and drawbacks.
As an enhancement, a new net methodology that enables automation and the capability to execute tracing beyond first-level transistors is introduced. This approach could potentially eliminate manual net tracing and significantly improves the overall failure analysis turnaround time. S
Since the introductionof the sub-45 nm technology, there have been increasing occurrences of complex fails such as structural, functional or soft fails, to name a few. Unlike parametric or power rail-related fails whose defects are fundamentally static in nature, a direct physical inspection following global fault isolation (FI) is not recommended for such complex fails. The localized signals no longer pinpoint the exact defect site or electrical weak point. In order to fulfil the mission of global FI, which is to narrow the search area for physical inspection to as small and accurate as possible, a layout net trace is needed.
Automated Multi-level Circuit Net Trace for Hotspot Analysis
S.H. Goh, E. Susanto, Song Li, B.L. Yeoh, M.H. Thor, Global Foundries, Product Diagnostic Engineering, Singapore
D. Zhou, Mentor – A Siemens Business
