Duke University, Durham, N.C., announces that its researchers have introduced probing solutions that may enable pre-bond and post-bond testing of through-silicon vias and logic dies used in manufacturing semiconductor components. They have also developed a test-architecture optimization and test scheduling solution that minimizes test time by considering various stages of 3D assembly. The Duke team has also introduced design-for-test innovations for 3D stacked chip technologies.
Sponsored by Semiconductor Research Corporation, Research Triangle Park, N.C., the research focuses on testing of 3D integration, since testing remains an obstacle that hinders mainstream adoption and mass manufacturing of 3D technology.
Specifically, it is paramount to stack “known good dies” to ensure a high manufacturing yield with stacked technology. However, due to the small feature sizes of TSVs and micro-bumps, it is extremely difficulty to probe wafers at a pre-bond stage. The Duke team has presented an innovative solution to this problem by probing multiple micro-bumps at the same time, thereby shorting TSVs and forming a TSV network. Aggregated measurements from TSV networks can then be used to detect defects in TSVs as well as in the die logic.
Furthermore, by developing the DFT structures that must be included on the die and the measurement infrastructure needed on the probe cards, the research demonstrates that the proposed approach is robust to process variations as well variations in contact resistance to the potentially non-uniform nature of probe contacts.
Next, in the area of post-bond testing, the Duke team developed a test-architecture optimization and test scheduling solution that minimizes test time by considering various stages of 3D assembly. The research included formal models based on integer linear programming as well as fast heuristic solutions. An especially innovative aspect of this research is its solution for recovering the delay overhead introduced by the DFT that is added for 3D stack testing.
“We have shown that retiming can be used to redistribute the slack on critical paths, whereby the delay overhead due to 3D DFT can be reduced to zero. This is a remarkable research breakthrough, which shows that there is something called a ‘free lunch’ after all,” said Brandon Noia, a Ph.D. student who was part of the Duke team and a recipient of the SRC Ph.D. Fellowship. Now graduated and part of SRC member company AMD, Dr. Noia also received the European Design and Automation Association 2014 Outstanding Dissertation Award for this research.
https://www.src.org/newsroom/press-release/2015/722/
