Samsung Electronics Co. Ltd., Korea, has begun mass producing the industry’s first 10-nm class 8Gb DDR4 (double-data-rate-4) DRAM chips and the modules derived from them. The new chips significantly improve the wafer productivity of 20nm 8Gb DDR4 DRAM by more than 30%.
The industry-first 10nm-class DRAM is the result of Samsung’s advanced memory design and manufacturing technology integration. To achieve an extremely high level of DRAM scalability, Samsung has taken its technological innovation one step further than what was used for 20nm DRAM. Key technology developments include improvements in proprietary cell design technology, QPT (quadruple patterning technology) lithography, and ultra-thin dielectric layer deposition.
DDR4 is quickly becoming the most widely produced memory for personal computers and IT networks in the world, and Samsung’s latest advancement will help to accelerate the industry-wide shift to advanced DDR4 products.
Samsung enabled 10nm-class DRAM for the first time in the industry after overcoming technical challenges in DRAM scaling. These challenges were mastered with ArF immersion lithography, which does not require EUV equipment.
Samsung’s roll-out of the 10nm-class (1x) DRAM marks yet another milestone for the company after it first mass produced 20nm 4Gb DDR3 DRAM in 2014.
“Samsung’s 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry,” said Young-Hyun Jun, President of Memory Business, Samsung Electronics. “In the near future, we will launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users.”
The new DRAM supports a data transfer rate of 3200 megabits per second (Mbps), which is more than 30% faster than the 2400 Mbps rate of 20nm DDR4 DRAM. Also, new modules produced from the 10nm-class DRAM chips consume 10 to 20% less power, compared to their 20nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems.
