Mentor Graphics Corp., Wilsonville, Ore., announces that its 3D-IC flow solutions have been validated by TSMC with a true 3D stacking test vehicle for TSMC’s 3D-IC Reference Flow. The flow expands support from silicon interposer offerings to include TSV-based, stacked die designs. Specific Mentor offerings include capabilities for metal routing and bump implementation, multi-chip physical verification and connectivity checking, chip interface and TSV parasitics extraction, thermal simulation, and comprehensive pre- and post-package testing.
The Mentor Graphics 3D-IC flow for TSMC provides a rich set of enhancements across the Mentor IC product portfolio. The Olympus-SoC place and route system serves as the 3D-IC physical design cockpit for both silicon interposer- and TSV-based designs with support for cross-die bump mapping and checking; TSV, microbump, and backside metal routing; and copper pillar bump implementations.
The Pyxis IC Station custom layout product provides schematic-driven layout that supports a TSV design flow. It also enables both orthogonal and 45-degree redistribution layer (RDL) routing. Specific enhancements for the TSMC 3D-IC flow include improvements to the bump file import process.
Whether the designer is working in a custom or digital design cockpit, the Calibre nmDRC and Calibre nmLVS products provide inter-die design rule and layout vs. schematic checking, including IO alignment accuracy verification, and connectivity checking for double-sided bumps using either DEF or GDS input. The Calibre xRC™ and Calibre xACT™ products extract parasitics for backside routing and single- or double-sided bumps defined in DEF or GDS formats. They also handle TSV-to-TSV coupling extraction to drive static timing analysis and SPICE simulations, and generate TSV sub-circuit equivalents for multi-die parasitic models.
