Cadence Design Systems, San Jose, Calif., introduces the Modus Test Solution, a product that reportedly enables design engineers to reduce test time by up to a factor of three, thereby reducing production test cost and increasing silicon profit margins. This next-generation test solution incorporates patent-pending, physically aware 2D Elastic Compression architecture that enables compression ratios beyond 400X without impacting design size or routing.
Scan compression logic forms a physically aware two-dimensional grid across the chip floorplan, enabling higher compression ratios with reduced wire length. At 100X compression ratios, wire length for 2D compression can be up to 2.6X smaller than current industry scan compression architectures.
Registers embedded in the decompression logic enable fault coverage to be maintained at compression ratios beyond 400X by controlling care bits sequentially across multiple scan cycles during automatic test pattern generation (ATPG).
A shared test access bus can be inserted to perform at-speed programmable memory built-in self test (PMBIST) across multiple embedded memories in an IP core. New soft programmable test algorithms for FinFET SRAMs and automotive safety applications are also included with this feature.
Design for test (DFT) logic insertion and ATPG capabilities use a new, unified Tcl scripting and debug environment that is shared with the Cadence Genus Synthesis Solution, the Innovus Implementation System and the Tempus Timing Signoff Solution.
Modus shares a Tcl scripting and debugging environment with Cadence’s Genus Synthesis Solution, Innovus Implementation Solution, and Tempus Timing Signoff Solution, according to the company.
Its other capabilities include 2D compression, elastic compression, and embedded memory bus support. Modus incorporates automatic test pattern generation, built-in self-test, and design-for-test technologies. It provides up to 3X reduction in test time without impacting design size or fault coverage. It also enables up to 2.6X reduction in compression logic wirelength. It is natively integrated with the Genus Synthesis Solution.
The company is focused on the concept of a single user interface for Modus and its related design tools, because with a common interface, different steps in the chip design, manufacturing, and testing processes can be like different apps on an iPhone.
