Engineers from ON Semiconductor presented a discussion of the electro-optical probing technique for failure analysis at the wafer and die level, at the ASM International ISTFA 2019 conference in Portland, Oregon.
Given the challenges FA Engineers have in fault localization, top-side analysis is facing a major challenge with today’s advanced packaging and shrinking of die sizes. At the wafer and die level it is relatively easy to probe with little or no sample preparation. Greater challenges occur after the die is packaged. The difficulty further lies in nondestructively analyzing the die. Another issue with failure analysis is accurately deprocessing the device for probe pad deposition.
Techniques such as electro-optical probing (EOP) or laser voltage probing (LVP) acquire electrical signals on transistors and create an activity map of the circuitry. In failure analysis, it is applied to localize defects.
This paper discusses integrating EOP techniques in traditional FA to localized failure in mixed signal ICs. Three case studies were presented in this paper to establish the technique to be effective, quick, and easy to probe non-invasively with minimal backside sample preparation.
The most significant benefit of EOP is the accessibility of the nodes with minimal sample preparation. For example, there is no need of a probe pad, and simple backside thinning is sufficient. This makes EOP a much faster, nondestructive, contactless analysis technique.
EOP is a very versatile technique that has proven to be useful on many different devices (analog devices, MOSFETs, scan failures). In this paper, we evaluated better ways to analyze clock skew delay, abnormal transistor switching and clock shootthrough by applying EOP for acquiring timing and fault information.
Case Studies on Application of Electro Optical Probing (EOP) – A Noninvasive Backside Localization Technique in Failure Analysis
Srinath Rajaram, Rajesh Kabadi, and Eric Barbian
Product Analysis Lab, ON Semiconductor, Phoenix, Arizona
