Cadence Design Systems Inc., San Jose, Calif., has developed the Cadence Perspec System Verifier platform, a software-driven system-on-chip (SoC) verification solution. It is designed for use-case, scenario-based, software-driven SoC verification. Intuitive graphical specification of system-level verification scenarios, and a definition of the SoC topology and actions, enable up to ten times productivity improvement versus typical manual test development.
It automates system-level, coverage-driven test development using constraint-solving technology. A part of the Cadence System Development Suite, Perspec System Verifier reduces complex test development from weeks to days, while also allowing design teams to reproduce, find, and fix complex bugs to improve overall SoC quality. A Unified Modeling Language (UML) based view of system-level actions and resources that, combined with powerful solver technology, creates an intuitive view of complex and hard-to-test system-level use-case interactions.
Solver technology automates the generation of portable tests to deliver complete coverage of system-level scenarios based on chip constraints and the scope of the scenarios, to verify SoC-level features for functionality, performance and power.
Tests run on all pre-silicon verification platforms including simulation, acceleration, and emulation, as well as virtual and FPGA prototyping, can be further used to validate actual silicon
