Cadence Design Systems Inc., San Jose, Calif., introduces a faster version of the Incisive functional verification platform. Addressing both intellectual property (IP) block-to-chip and system-on-chip (SoC) verification challenges, the Incisive 13.2 platform offers orders of magnitude faster performance with two new engines and additional automation features to speed SoC verification closure.
For IP block-to-chip verification, some enhancements include:
New Trident engine in the Incisive Formal Verifier and the Incisive Enterprise Verifier, which improves formal analysis performance up to 20X;
New constraint engine in the Incisive Enterprise Simulator that speeds UVM and SystemVerilog testbench simulation;
New SystemVerilog support in Incisive Debug Analyzer;
And unique UVM debug capabilities and optimized probing in the SimVision debug environment inside Incisive Enterprise Simulator that reduces database size by up to 10X.
For SoC verification, some enhancements include:
Comprehensive x-propagation support in the Incisive Enterprise Simulator and the Incisive Enterprise Verifier to speed SoC reset and low-power simulations up to 5X;
And new support for SystemVerilog IEEE 1800-2012 real number modeling in the Incisive Digital Mixed Signal option for faster mixed-signal simulation over 100X.
