The Georgia Institute of Technology, Atlanta, reports that its researchers have developed a technology for cooling transistors that is based on de-ionized water flowing through microfluidic passages. Combined with connection technology that operates through structures in the cooling passages, the new technologies could allow development of denser and more powerful integrated electronic systems that would no longer require heat sinks or cooling fans on top of the integrated circuits.
To make their liquid cooling system, Prof. Muhannad Bakir and graduate student Thomas Sarvey removed the heat sink and heat-spreading materials from the backs of stock Altera FPGA chips. They then etched cooling passages into the silicon, incorporating silicon cylinders approximately 100 microns in diameter to improve heat transmission into the liquid. A silicon layer was then placed over the flow passages, and ports were attached for the connection of water tubes.
In multiple tests, a liquid-cooled FPGA was operated using a custom processor architecture provided by Altera. With a water inlet temperature of approximately 20°C and an inlet flow rate of 147 ml/min, the liquid-cooled FPGA operated at a temperature of less than 24°C, compared to an air-cooled device that operated at 60°C.
In addition to improving overall cooling, the system could reduce hotspots in circuits by applying cooling much closer to the power source. Eliminating the heat sink could allow more compact packaging of electronic devices – but only if electrical connection issues are also addressed.
Supported by the Defense Advanced Research Projects Agency (DARPA), the research is believed to be the first example of liquid cooling directly on an operating high-performance CMOS chip. Details of the research were presented on September 28 at the IEEE Custom Integrated Circuits Conference in San Jose, Calif.
In a separate research project, Prof. Bakir’s group has demonstrated the fabrication of copper vias that would run through the silicon columns that are part of the cooling structure fabricated on the FPGAs. Graduate student Hanju Oh, co-advised with College of Engineering Dean Gary May, fabricated high aspect ratio copper vias through the silicon columns, reducing the capacitance of the connections that would carry signals between chips in an array.
http://www.rh.gatech.edu/news/455491/liquid-cooling-moves-chip-denser-electronics
