Silicon transistors, essential for amplifying and switching signals in electronic devices from smartphones to automobiles, face a fundamental physical limit known as “Boltzmann tyranny,” which prevents them from operating below a certain voltage and hinders energy efficiency. This is particularly problematic with the rapid development of AI technologies that require faster computation. To overcome this limit, MIT researchers have developed a new type of three-dimensional transistor using ultrathin semiconductor materials. These devices, featuring vertical nanowires only a few nanometers wide, can match the performance of state-of-the-art silicon transistors while operating efficiently at much lower voltages.

“This is a technology with the potential to replace silicon, so you could use it with all the functions that silicon currently has, but with much better energy efficiency,” says Yanjie Shao, an MIT postdoc and lead researcher.

The transistors leverage quantum mechanical properties to simultaneously achieve low-voltage operation and high performance within an area of just a few square nanometers. Their extremely small size would enable more of these 3D transistors to be packed onto a computer chip, resulting in fast, powerful electronics that are also more energy-efficient.

In electronic devices, silicon transistors often operate as switches. Applying a voltage to the transistor causes electrons to move over an energy barrier from one side to another, switching the transistor from “off” to “on.” By switching, transistors represent binary digits to perform computation.

A transistor’s switching slope reflects the sharpness of the “off” to “on” transition. The steeper the slope, the less voltage is needed to turn on the transistor and the greater its energy efficiency.

However, because electrons move across an energy barrier, Boltzmann tyranny requires a certain minimum voltage to switch the transistor at room temperature.

To overcome silicon’s physical limit, the MIT researchers used a different set of semiconductor materials—gallium antimonide and indium arsenide—and designed their devices to leverage a unique phenomenon in quantum mechanics called quantum tunneling.

Quantum tunneling is electrons’ ability to penetrate barriers. The researchers fabricated tunneling transistors, which leverage this property to encourage electrons to push through the energy barrier rather than go over it.

But while tunneling transistors can enable sharp switching slopes, they typically operate with low current, which hampers the performance of an electronic device. Higher current is necessary to create powerful transistor switches for demanding applications.

Using tools at MIT.nano, MIT’s state-of-the-art facility for nanoscale research, the engineers were able to carefully control the 3D geometry of their transistors, creating vertical nanowire heterostructures with a diameter of only 6 nanometers. They believe these are the smallest 3D transistors reported to date.

Such precise engineering enabled them to achieve a sharp switching slope and high current simultaneously. This is possible because of a phenomenon called quantum confinement.

Quantum confinement occurs when an electron is confined to a space that is so small that it can’t move around. When this happens, the effective mass of the electron and the properties of the material change, enabling stronger tunneling of the electron through a barrier.

Because the transistors are so small, the researchers can engineer a very strong quantum confinement effect while also fabricating an extremely thin barrier.

Precisely fabricating devices that were small enough to accomplish this was a major challenge.

When the researchers tested their devices, the sharpness of the switching slope was below the fundamental limit that can be achieved with conventional silicon transistors. Their devices also performed about 20 times better than similar tunneling transistors.

The researchers are now striving to enhance their fabrication methods to make transistors more uniform across an entire chip. With such small devices, even a 1-nanometer variance can change the behavior of the electrons and affect device operation.

They are also exploring vertical fin-shaped structures, in addition to vertical nanowire transistors, which could potentially improve the uniformity of devices on a chip.

For More Information: Nature Electronics

Image: Ultra-scaled vertical-nanowire device design.

Layered assembly of 2D materials such as graphene has potential roles in the development of new electronic devices. Manufacturing these materials at a large scale while making them atomically clean is a major challenge. This new cleaning mechanism is an important tool. It will help researchers develop manufacturing protocols for large area, high-quality devices. It will also streamline the production of these materials by removing the need for additional processes after they are cleaned.

Researchers from New York University and the Center for Functional Nanomaterials (CFN), a Department of Energy Office of Science user facility at Brookhaven National Laboratory, used the CFN Quantum Material Press (QPress) to assemble 2D graphene heterostructures materials. This study showed that the interface cleaning process of layered heterostructures made from contaminated 2D layers involves more complex mechanisms than a simple thermal actuation that is typically used to make clean interfaces. The combination of non-bonding interactions of the polymer with graphene, thermally activated mobilization of polymer residues, and mechanical actuation is essential for fabricating heterostructures with atomically clean interfaces from polyvinyl acetate-contaminated graphene. This study opened a new opportunity to develop a more effective process to make large and clean layered heterostructure devices.

For more information: Small

Image: Robotic stacking of 2D material layers on a heated substrate while applying pressure pushes out residues such as polymers from between the layers, resulting in atomically clean interfaces between layers.

“It’s exciting to expand our reach to strengthen already existing relationships, as we have had with FSU and FAMU, and create new partnerships we hope will continue for many years,” said Jens Dilling, associate laboratory director for Neutron Sciences at ORNL. “This is all to the benefit of ORNL, our university collaborators and, most importantly, to the benefit of science. We are thrilled to bring the wonder of neutrons to a new generation of undergraduate and graduate students and help faculty grow their science and technology impact.”

The goals of the ORNL Neutron Nexus program are to foster professional and personal relationships, widen neutron science educational opportunities, organize in-person visits to ORNL for students and faculty, organize on-site presence for remote experiments, increase engagement for technical and scientific support, and set up physical space commitments between ORNL and a regional collection of colleges and universities, including Minority Serving Institutions (MSIs), community colleges, and technical colleges.

A planned Department of Materials Science and Engineering at the joint college is part of the inaugural Neutron Nexus, as ORNL “brings neutrons” to northern Florida, enabling new users to leverage cutting-edge neutron scattering and imaging capabilities to transform their research.

The special relationship between the two universities as the “parents” of the nation’s only joint college of engineering, and the unique model of the college itself, benefits the pilot Nexus program.

For More Information: FAMU-FSU College of Engineering

Image: FAMU-FSU College of Engineering Dean Suvranu De speaks at the ORNL Days 2024 Power of Partnership Reception held at the High-Performance Materials Institute in the Materials Research Building of the FAMU-FSU College of Engineering in Tallahassee, Florida.