Researchers from Google, Mountain View, Calif., and Delft University of Technology, Netherlands, have developed a novel failure analysis hardware and sample preparation solution that enables system-level failure analysis on mobile 3D integrated circuits. The paper was published in Microelectronics Reliability.
The paper presents a novel failure analysis (FA) hardware and sample preparation solution that enables system-level FA on mobile system-on-a-chip (SoC) PoP devices, where the DRAM is stacked atop the logic controller device. The primary challenge in performing electrical fault isolation on the bottom die is providing direct line-of-sight (LoS) access while preserving the top DRAM functionality through extremely small interconnects called through interposer vias (TIVs).
For the first time, this groundbreaking hardware solution overcomes the challenge of connecting a DRAM atop the SoC silicon. It uses the smallest possible interposer pin pitch (∼210 um) and an advanced DRAM card design that incorporates stringent design rules to enable up to 6.3 Gbps using a DDR training test and runs standard Android stress applications.
This novel solution paves the way for the failure analysis of 3D IC devices on a system level platform. These devices are not only used in mobile applications, but also for cloud, server, and quantum computing ICs assembled in complex packages.
Image – Courtesy of Creative Commons.
For more information:
Delft University of Technology
https://www.tudelft.nl/en/
