A 0.42-nanometer breakthrough could push transistors beyond silicon

A working transistor requires an extremely thin insulating layer known as the gate dielectric. This layer sits above the semiconductor and helps control the movement of electrons. As transistors shrink, making this insulating layer thinner can improve electrical control. The difficulty is that adding such layers to atomically thin semiconductors can disturb the delicate interface between the materials. That disruption can scatter electrons and erase some of the performance gains engineers are trying to achieve.

For years, researchers have therefore faced a difficult tradeoff. They could strengthen control over the transistor gate, or they could protect the mobility of the charge carriers moving through the device. Achieving both at once has been much harder.

Researchers at National Yang Ming Chiao Tung University (NYCU), Taiwan, working with TSMC Corporate Research, Taiwan, have now demonstrated a new way to address this problem by focusing on the interface itself.

The work, published in Nature Electronics, shows that carefully controlling the atomic boundary between a semiconductor and its insulating layer can allow the dielectric to be made extremely thin while maintaining strong electrical performance. Rather than searching for a completely different semiconductor, the researchers concentrated on the narrow region where the two materials meet, an area only a few atoms thick.

Instead of changing either the semiconductor or the gate dielectric, the NYCU researchers redesigned the interface connecting them.

The team first placed an ultrathin epitaxial aluminum layer directly onto monolayer molybdenum disulfide (MoS2). They then carefully oxidized the aluminum, producing an aluminum oxide layer about 0.42 nanometers thick. After that, they added the high κ hafnium oxide gate dielectric.

Despite being only a fraction of a nanometer thick, the engineered interface performs two important jobs.

First, it creates a smooth and continuous surface that allows the hafnium oxide to grow more uniformly over the MoS2. Second, it works as an atomic buffer that limits unwanted electrical interactions between the dielectric and the semiconductor. This protection helps electrons continue moving efficiently through the transistor channel.

In this design, the interface does more than simply keep two materials apart. It becomes a functional part of the transistor and helps the materials work together more effectively.
Using the new interface design, the researchers fabricated short-channel top-gate transistors from CVD-grown monolayer MoS2. The devices had an equivalent oxide thickness of roughly one nanometer.

Testing showed low leakage current, minimal hysteresis, and maximum transconductance of 0.45 mS μm-1 in transistors with channels measuring about 100 nanometers.

More importantly, the devices demonstrated a combination that has been difficult to achieve in atomically thin transistors: very thin dielectric scaling, strong electrostatic control, and sustained carrier transport.

Because the researchers used CVD-grown monolayer MoS2 rather than mechanically exfoliated flakes, they believe the approach brings the technology closer to materials and processes that could eventually be suitable for wafer-scale manufacturing.

The findings also point to a broader change in the way semiconductor researchers think about transistor design.

For decades, much of the effort to improve transistors has centered on discovering better semiconductor materials or making devices smaller. As transistor components approach atomic dimensions, however, the interfaces separating different materials become increasingly important.

These regions may be only a few atoms thick, yet they can strongly influence how well the materials on either side work together. The new results add to growing evidence that controlling these atomic interfaces could become as important as developing new semiconductor materials themselves.

 

Image – Researchers from NYCU and TSMC show that redefining the atomic boundary between materials can address a major engineering barrier restricting the development of next-generation semiconductor devices. Courtesy of: Springer Nature.

 

For more information:

National Yang Ming Chiao Tung University
https://www.nycu.edu.tw/nycu/en/index

New analog memory may make smart devices even smarter

Researchers at Sandia National Laboratories have developed electro-thermo-chemical random-access memory, a technology that uses localized heating and electrical pulses to store a range of analog values instead of binary ones and zeros, making future electronics more energy efficient.

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Detecting ultra-low sulfur levels in superalloys

LECO Corporation, St. Joseph, Mich., has demonstrated how its CS844ES elemental analyzer enables accurate determination of sulfur at levels as low as 0.1 µg in steel, nickel, and superalloys, extending the combustion technique to sensitivities previously unachievable

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TESCAN expands its presence in Asia

Czech-based electron microscope manufacturer TESCAN plans to establish a local subsidiary in Taiwan in 2025 to meet rising demand from semiconductor clients across the Asia-Pacific region.

Founded in Brno, the Czech Republic’s second-largest city, TESCAN built its reputation over three decades in fields like materials science and geoscience. In recent years, however, the company has pivoted toward the semiconductor industry, with a particular focus on the rapidly expanding advanced packaging segment.

TESCAN’s advanced packaging FA solution is built around a hybrid workflow that integrates scanning electron microscopy (SEM), focused ion beam (FIB), and other inspection tools into a seamless, cross-platform system. The setup aims to reduce testing time, cut labor requirements, and speed up R&D while improving yield outcomes.

Described as a “full-body checkup” for chips, the solution uses a suite of diagnostic tools—much like a team of medical specialists—to identify failure points across materials and structures. This approach has proven essential for OSAT providers, foundries, and IC design houses alike.

According to TESCAN Taiwan country manager Robert Feng, FA begins with non-destructive testing to locate potential defects without damaging the sample. The next phase involves destructive analysis using laser cutting for speed, followed by dual-beam systems to isolate and expose the faulty regions.

The process continues with SEM imaging via the dual-beam system to analyze interfaces and defect signatures. To address the rising need for structural stress and material composition analysis, TESCAN also provides a 4D STEM-enabled platform that measures internal stress fields and compositional shifts, supporting both process refinement and next-gen packaging evolution.
TESCAN’s semiconductor strategy—centered on failure analysis and advanced packaging—is gaining momentum thanks to integrated technologies and region-specific applications.

According to APAC managing director Sean Lee, the semiconductor business in Asia-Pacific contributed nearly 50% of the company’s global revenue in 2024. “There’s still plenty of room to grow,” he said.

For 2025, Lee projects a 40% revenue surge in APAC, fueled largely by Chinese demand, with semiconductor-related sales expected to account for about half of that growth.

As a challenger in the semiconductor equipment space, TESCAN is still trailing global leaders in market share. To gain ground, the company is leaning into product flexibility and differentiation.

Lee highlights technologies such as CoWoS, 2.5D/3D, and heterogeneous integration as major drivers of increased FA complexity. TESCAN’s strategy focuses on large-format and customized inspection demands, delivering broader and deeper coverage tailored to client-specific requirements.
TESCAN’s edge, Lee says, lies in its singular focus: “We only do electron microscopes.” Unlike competitors with sprawling product portfolios, the company offers more streamlined and responsive collaboration.

Most equipment vendors favor standardized models to maximize cost and production efficiency. TESCAN, however, starts with the unmet needs of leading customers and gradually scales into more price-sensitive segments—a strategy built on flexibility and differentiation.

Across the region, Lee says, packaging customers want FA tools that are faster, more precise, and competitively priced. TESCAN has targeted sample preparation, the bottleneck in the testing workflow, and introduced AI and machine learning to streamline it. The result: faster output, fewer manual errors, and relief for an industry plagued by skilled labor shortages.

Feng notes that training an operator in sample preparation and analysis typically takes six to twelve months. But with product lifecycles shrinking, delays are no longer acceptable. TESCAN’s solution reduces prep time from four hours to under one, even for first-time users.

Lee points out that Taiwan and China together account for over 70% of the global advanced packaging market. Many Chinese customers are Taiwan-owned or managed by Taiwanese executives, making Greater China the most critical hub for packaging technology and a core driver of TESCAN’s APAC expansion.

Although Lee concedes that launching the Taiwan office in 2025 is “a beat late” and would have been better timed two years earlier, he believes conditions remain favorable. As client technologies mature and US-China chip tensions intensify, China’s localization drive makes this an opportune moment.

Following the acquisitions of TESCAN Korea and anti-vibration system maker Daeil Microanalysis Laboratory (DML), the company will open new subsidiaries in Taiwan and Singapore in 2025. Moving away from agent-based distribution marks a major step in strengthening brand visibility and service capabilities across the APAC semiconductor market.

In the past, Taiwan clients relied on local agents for sales and service, which created delays in communicating feedback to TESCAN’s R&D hub in the Czech Republic, slowing development and impeding local adaptation.

To avoid missing out on co-innovation opportunities, TESCAN opted to establish its subsidiaries, enabling technical teams to work directly with clients. This move shortens communication loops, accelerates market responsiveness, and enhances local support across key APAC markets—including Taiwan, China, South Korea, and Malaysia—while deepening regional collaboration.

 

Image – Sean Lee (L) and Robert Feng (R). Courtesy of: DIGITIMES.

 

For more information:
TESCAN
https://www.tescan.com/