User Groups

The ISTFA 2026 User Group Sessions offer an engaging platform for professionals to discuss and share insights on the latest trends in failure analysis. Covering seven distinct areas, these interactive sessions immerse attendees in a collaborative environment focused on innovation and knowledge sharing. It is an ideal opportunity for participants to enhance their expertise, tackle industry challenges together, and drive advancements in the field. Notably, three of this year’s sessions are scheduled back-to-back with corresponding topics from the International Roadmap for Failure Analysis (IRFA).

Optical Fault Isolation/Test and Diagnostics User Group

Monday, October 5, 2026: 4:00 – 5:00 PM

Moderators:
Dan Bockelman, Intel Corporation
Dan Bodoh, NXP Semiconductors
Munindhran Rao, Cirrus Logic
Arun Karunanithi, AMD

The Optical Fault Isolation, Test, and Diagnosis User Group will include discussions on a variety of topics related to optical probing techniques for fault isolation as well as test and diagnosis. The format will be open discussion with opportunities for audience participation.

Examples of discussion topics include:

Improvements in Diagnosis

LIT Techniques

Laser-based Techniques

Techniques for Backside Power Delivery FI

Impact of AI in Optical FI and Diagnosis

Integrated PFA User Group

Monday, October 5, 2026: 4:00 – 5:00 PM

Moderators:
Pawel Nowakowski, Fischione Instruments
Craig Nakakura, Sandia National Laboratory
Rosine Coq Germanicus, UNICAEN

As semiconductor technologies continue to evolve, physical failure analysis has become increasingly dependent on integrating multiple analytical techniques rather than relying on a single method. Identifying the root cause of a failure now requires not only the right analytical tools, but also the right analytical strategy.

Join us for an interactive discussion focused on the integration of electrical characterization, de-processing, imaging, materials analysis, and nanoscale characterization into efficient and effective failure analysis workflows. Through short presentations and open discussion, participants will share challenging cases, discuss workflow bottlenecks, and exchange practical experiences that help transform electrical anomalies into definitive physical root causes.

Discussion Topics:

Workflow Optimization – Developing decision-making strategies that improve efficiency, reduce analysis time, and maximize the likelihood of success, includingidentifyingthe essential analytical techniques and when they provide the greatest value.
From Electrical Failure to Physical Root Cause – How do we choose the most effective analytical path while minimizing unnecessary sample preparation and analysis?
Cross-Correlated Analysis – Integrating electrical characterization, imaging, de-processing, microscopy, spectroscopy, and nanoscale techniques to build confidence in root cause identification.
Workflow Optimization – Developing decision-making strategies that improve efficiency, reduce analysis time, and maximize the likelihood of success.
Advanced Packaging Challenges – Addressing analytical complexities associated with chiplets, 2.5D/3D integration, hybrid bonding, backside power delivery, and heterogeneous integration.
Lessons Learned – Open discussion of difficult cases, unexpected obstacles, and practical solutions from the failure analysis community.

Whether you work in failure analysis, process integration, analytical microscopy, or materials characterization, this User Group provides an opportunity to exchange ideas, discuss real-world challenges, and help define best practices for integrated physical failure analysis in next-generation semiconductor technologies.

System in Package User Group

Monday, October 5, 2026: 4:00 – 5:00 PM

Moderators:
Hemachandar “Chandu” Tanukonda, Intel Corporation
Jer O’Sullivan, Analog Devices
Bernice Zee, AMD

As advanced packaging technologies continue to evolve, System in Package (SiP) architectures are enabling unprecedented levels of heterogeneous integration, performance, and functionality. However, the increasing complexity of chiplet-based systems, high-bandwidth memory integration, advanced interconnects, and large-form-factor packages is creating new challenges for failure analysis and debug. In support of this year’s ISTFA theme, “Design for Analysis,” this user group will explore emerging gaps, industry pain points, and innovative approaches that are shaping the future of analysis and characterization of advanced SiP products. Through invited talks and interactive audience discussions, participants will have the opportunity to share experiences, discuss solutions, and identify future needs for the FA community.

As the semiconductor industry continues to adopt increasingly complex packaging architectures, traditional failure analysis workflows are being challenged by reduced physical access, higher device integration, greater power densities, and shrinking interconnect dimensions. New package architectures often combine multiple dies, process technologies, memory stacks, and specialized accelerators within a single package, creating additional layers of complexity for root-cause identification and fault localization. These developments are driving the need for new methodologies, improved design-for-analysis strategies, and enhanced collaboration between design, manufacturing, reliability, test, and failure analysis teams.

This session will feature invited presentations and audience-driven discussions focused on practical challenges and emerging solutions in the analysis of advanced packaging technologies. Particular emphasis will be placed on non-destructive inspection techniques, acoustic imaging, 3DXRAY imaging, and the unique challenges associated with high-power and AI-driven products. Attendees will also have the opportunity to participate in live polling and open discussions to exchange ideas, benchmark industry practices, and identify key technology gaps that may influence future tool development and analysis methodologies.

Whether your organization is developing, manufacturing, or analyzing advanced packaging solutions, this session provides a forum to discuss common challenges, share lessons learned, and explore future directions for SiP failure analysis and characterization.

Topics for the System in Package User Group, ISTFA 2026 include:

State of SiP Landscape

Emerging Failure Analysis Challenges Not Yet Solved

Design for Analysis in Advanced Packaging

Acoustic Imaging (CSAM) Challenges and Opportunities

3D X-ray and Non-Destructive Imaging Advances

High-Power Product Failure Analysis

Future Direction for SiP

Sample Preparation User Group

Tuesday, October 6, 2026: 12:50 – 1:50 PM

Sponsored By:

Moderators:
Jim Colvin, FA Instruments, Inc.
Chris Richardson, Allied High Tech
Rosalinda Ring, Neno Vision
Bryan Tracy, ibss Group
Nathan Bakken, Intel

As technologies push device complexity to its limits, the demand for high-quality, defect-free sample preparation has never been more critical. Breakthroughs like backside power delivery networks (BPDN) and 3D heterogeneous integration offer massive performance gains but they also block traditional physical and optical diagnostic paths. To survive this shift, the industry must transition from reactive troubleshooting to Design for Failure Analysis (DFA). We can no longer treat sample preparation as an afterthought; we must design devices so they can actually be prepared and analyzed.

Our failure analysis lab’s sample preparation capabilities are hitting a physical wall with modern device architectures. Delayering advanced nodes now means handling fragile materials, ultra-thin layers, and delicate nanoscale features without causing structural collapse, while BPDN buries active silicon beneath complex metal networks. This forces us to adapt our mechanical and plasma deprocessing workflows for the die’s most complex side. At the same time, we must achieve uniform, artifact-free silicide removal on legacy devices, and map localized strain across dense packaging interfaces. Overcoming these hurdles requires a dual approach: advancing our physical deprocessing while actively using DFA principles to ensure these complex structures can survive the prep process.

Join our Sample Preparation User Group for an interactive discussion on the next wave of sample prep workflows, DFA-driven layouts, and localized strain-measurement techniques. This is your forum to share practical insights, troubleshoot tricky lab prep work, and explore what’s next.

The Sample Prep User Group Mission: If a device cannot be prepared, it cannot be analyzed. By bridging the gap between chip design and the prep lab, we ensure the diagnostics of tomorrow remain possible.

Don’t miss this opportunity to connect with fellow sample prep engineers, lab managers, and DFA advocates. Bring your toughest sample prep hurdles, share your custom lab recipes, and leave with practical solutions to your daily deprocessing challenges.

Focused Ion Beam User Group

Tuesday, October 6, 2026: 1:50 – 2:50 PM

Moderators: 
Valerie Brogden, Covalent Metrology
Steven Herschbein, Independent Consultant
Edward Principe, Synchrotron Research
Michael Wong, Thermo Fisher Scientific

Focused Ion Beam (FIB) technology is evolving rapidly—are you keeping up?

Modern FIB platforms are essential for failure analysis, semiconductor manufacturing, and research, enabling everything from cross-sectioning and high-resolution imaging to TEM sample preparation and circuit edit. New ion species, process gases, automation, and accessories continue to expand what’s possible while raising new questions about tool ownership, outsourcing, service models, and emerging device architectures.

Join the FIB community for this interactive 90-minute ISTFA session. Through a series of lightning talks and an open discussion, we’ll share real-world challenges, troubleshooting tips, and future directions for FIB technology.

Whether you’re a lab manager, tool operator, experienced user, or simply FIB-curious, everyone is welcome. Bring your questions, experiences, and ideas—this session is driven by the community, and your perspective matters.

Artificial Intelligence in Failure Analysis User Group

Tuesday, October 6, 2026: 4:00 – 5:00 PM

Moderators:
Konstantin Schekotihin, University Klagenfurt
Florian Felux, Infineon Technologies
Peter Hoffrogge, PVA Tepla
Christoph Maaier, Infineon Technologies
Michael Beetz, Infineon Technologies

AI in FA is growing far beyond finding defects in microscope images. Today, new software automatically plans electrical testing to isolate faults, analyzes test equipment log files, and performs temperature or stress mapping. Large language models serve as the “brains” of new smart assistants (agents) that can understand engineering instructions, plan complex workflows, and automatically run various lab tools, such as image search programs and database systems, to organize the entire diagnostic process. To support these capabilities, the AI User Group (AI UG) focuses on three areas of intelligence that enable these agents to work:

Ontology Definition: The rules and dictionaries agents use to understand instructions and plan diagnostic steps.

Data-Driven Pattern Learning: The software tools and ML models that agents can run to find defects in images, measurements, and logs.

Combined Reasoning: How agents connect these tools to engineering databases to explain the root cause of a failure.

However, daily lab operations face major challenges: scattered, uncleaned vendor data, a lack of data management (tracking origins and protecting design security), and difficulties connecting older tools.

The AI UG is bridging this gap through key standardization and cleanup initiatives:

Common Engineering Language (FA Ontology): We support the EU-driven effort (FA2IR/FA4.0 projects) to build a unified failure dictionary. This acts as a standard directory of failure causes that different lab tools can read.

SEMI Standardized Text Format: We promote a standardized text format (JSON) that attaches description tags to images and logs. This lets legacy equipment and automated systems process data automatically without manual reformatting.

Data Cleanup & Management: We establish simple guidelines for cleaning, labeling, and organizing records to prepare them for AI training while keeping sensitive design data safe.

Tool Integration: We connect these assistants with databases and software platforms to automate routine testing.

Nanoprobing/SPM User Group

Wednesday, October 7, 2026: 10:20 – 11:20 AM

Moderators:

Scott P. Lockledge, Ph.D., Tiptek LLC
Tad Daniels, Thermo Fisher Scientific
Ricky Anthony, Analog Devices

This year’s session highlights scanning probe microscopy (SPM) technique and is entitled “Scanning Probe Microscopy Electrical Techniques and Advanced Nanoprobing: The Importance of Sample Preparation”. SPM electrical characterization is important for advanced node semiconductor characterization and increasingly depends upon careful and proper preparation of samples to obtain useful results. For example, PFIB’s are often replacing traditional planar polishing to ensure precise planar delayering. These PFIB sample preparation methods enable SPM probes to make accurate and low resistance contacts for electrical characterization techniques.